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reg_sequence.ll
Commit message (
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Author
Age
*
ARM & AArch64: make use of common cmpxchg idioms after expansion
Tim Northover
2014-05-30
*
ARM: use LLVM IR to represent the vshrn operation
Tim Northover
2014-02-10
*
Revert "Tests: Be less dependent on a specific schedule/regalloc"
Matthias Braun
2013-10-11
*
Tests: Be less dependent on a specific schedule/regalloc
Matthias Braun
2013-10-11
*
ARM: implement some simple f64 materializations.
Tim Northover
2013-08-20
*
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to f...
Stephen Lin
2013-07-14
*
Make ARMAsmPrinter generate the correct alignment specifier syntax in instruc...
Kristof Beyls
2013-02-22
*
Enable the new coalescer algorithm by default.
Jakob Stoklund Olesen
2012-09-27
*
Try to make these tests more portable.
Evan Cheng
2012-09-20
*
Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte
Evan Cheng
2012-09-18
*
This commit contains a few changes that had to go in together.
Nadav Rotem
2012-04-01
*
ARM VLDR/VSTR instructions don't need a size suffix.
Jim Grosbach
2011-11-14
*
Simplify some uses of utohexstr.
Benjamin Kramer
2011-11-07
*
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ...
Owen Anderson
2011-07-15
*
Fix ARM tests to be register allocator independent.
Jakob Stoklund Olesen
2011-03-31
*
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
Evan Cheng
2010-12-05
*
Two sets of changes. Sorry they are intermingled.
Evan Cheng
2010-11-03
*
putback r116983 and fix simple-fp-encoding.ll tests
Andrew Trick
2010-10-21
*
Revert r116983, which is breaking all the buildbots.
Owen Anderson
2010-10-21
*
Add missing scheduling itineraries for transfers between core registers and V...
Evan Cheng
2010-10-21
*
Correct some load / store instruction itinerary mistakes:
Evan Cheng
2010-10-09
*
Change register allocation order for ARM VFP and NEON registers to put the
Bob Wilson
2010-10-08
*
Convert VLD1 and VLD2 instructions to use pseudo-instructions until
Bob Wilson
2010-09-02
*
Add alignment arguments to all the NEON load/store intrinsics.
Bob Wilson
2010-08-27
*
Replace some NEON vmovl intrinsic that I missed earlier.
Bob Wilson
2010-08-20
*
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
Bob Wilson
2010-07-13
*
Print "dregpair" NEON operands with a space between them, for readability and
Bob Wilson
2010-07-09
*
Reenable DAG combining for vector shuffles. It looks like it was temporarily
Bob Wilson
2010-07-09
*
Eliminate the other half of the BRCOND optimization, and update
Dan Gohman
2010-06-24
*
Remove arm_apcscc from the test files. It is the default and doing this
Rafael Espindola
2010-06-17
*
Fix some latency computation bugs: if the use is not a machine opcode do not ...
Evan Cheng
2010-05-28
*
Change ARM scheduling default to list-hybrid if the target supports floating ...
Evan Cheng
2010-05-21
*
TwoAddressInstructionPass doesn't really know how to merge live intervals when
Jakob Stoklund Olesen
2010-05-19
*
Fix PR7162: Use source register classes and sub-indices to determine the corr...
Evan Cheng
2010-05-18
*
Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG...
Evan Cheng
2010-05-17
*
Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ...
Evan Cheng
2010-05-17
*
Careful with reg_sequence coalescing to not to overwrite sub-register indices.
Evan Cheng
2010-05-17
*
Turn on -neon-reg-sequence by default.
Evan Cheng
2010-05-17
