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* Add some generic expansion logic for SMULO and UMULO. Fixes UMULO Eli Friedman2009-06-16
| | | | | | | | | | support for x86, and UMULO/SMULO for many architectures, including PPC (PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's not bad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73477 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman2009-06-04
| | | | | | | | | | | | | | | | integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 67132. This is breaking some objective-c apps.Evan Cheng2009-03-25
| | | | | | | Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67701 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't force promotion of return arguments on the callee.Rafael Espindola2009-03-17
| | | | | | | | | Some architectures (like x86) don't require it. This fixes bug 3779. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67132 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-03-17
| | | | | | | Revert inadvertent mis-fix of fneg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67084 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-03-17
| | | | | | | | | | | | | | - Fix fabs, fneg for f32 and f64. - Use BuildVectorSDNode.isConstantSplat, now that the functionality exists - Continue to improve i64 constant lowering. Lower certain special constants to the constant pool when they correspond to SPU's shufb instruction's special mask values. This avoids the overhead of performing a shuffle on a zero-filled vector just to get the special constant when the memory load suffices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-03-16
| | | | | | | | Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the llvm-gcc bootstrap a bit further along. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67048 91177308-0d34-0410-b5e6-96231b3b80d8
* Used "-enable-unsafe-fp-math" to allow this transformation - (a * b -c) = c ↵Mon P Wang2009-01-31
| | | | | | - a *b. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63475 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-26
| | | | | | | | | | | | | | | | | - Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't rely on grep -w working.Duncan Sands2009-01-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62682 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-21
| | | | | | | | | | | | | | - Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the private linkage.Rafael Espindola2009-01-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
* - Convert remaining i64 custom lowering into custom instruction emissionScott Michel2009-01-15
| | | | | | | | | | | | | | sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom DAG node types as needed. - i64 mul is now a legal instruction, but emits an instruction sequence that stretches tblgen and the imagination, as well as violating laws of several small countries and most southern US states (just kidding, but looking at a function with 80+ parameters is really weird and just plain wrong.) - Update tests as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62254 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix off-by-one error in traversing an array; this fixes a test.Misha Brukman2009-01-07
| | | | | | | The error was reported by gcc-4.3.0 during compilation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61896 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-06
| | | | | | | | | | | | | - Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we need to ensure that i128 is 16-byte aligned in real life), and 128 zero- extends are supported. - New td file: SPU128InstrInfo.td: this is where all new i128 support should be put in the future. - Continue to hammer on i64 operations and test cases; ensure that the only remaining problem will be i64 mul. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61784 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-05
| | | | | | | | - Teach SPU64InstrInfo.td about the remaining signed comparisons, update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61672 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-05
| | | | | | | - Add an 8-bit operation test, which doesn't do much at this point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61665 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-05
| | | | | | | | | | | - Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ. - Kill unused/unnecessary nodes in SPUNodes.td - Beef out the i64operations.c test harness to use a lot of unaligned loads, test loops and LLVM loop/basic block optimizations; run the test harness successfully on real Cell hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61664 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-03
| | | | | | | | | | - Remove custom lowering for BRCOND - Add remaining functionality for branches in SPUInstrInfo, such as branch condition reversal and load/store folding. Updated BrCond test to reflect branch reversal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61597 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3274: when promoting the condition of a BRCOND node,Duncan Sands2009-01-01
| | | | | | | | | | | promote from i1 all the way up to the canonical SetCC type. In order to discover an appropriate type to use, pass MVT::Other to getSetCCResultType. In order to be able to do this, change getSetCCResultType to take a type as an argument, not a value (this is also more logical). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
* This is not failing on Darwin for some reason. XFAIL for other platforms.Bill Wendling2008-12-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61533 91177308-0d34-0410-b5e6-96231b3b80d8
* XFAIL this for now until I can figure out what's going on.Scott Michel2008-12-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61512 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test erratum (which is wierd: works locally for me?)Scott Michel2008-12-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61511 91177308-0d34-0410-b5e6-96231b3b80d8
* - Start moving target-dependent nodes that could be represented by anScott Michel2008-12-30
| | | | | | | | | | | | | | instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
* - Remove Tilmann's custom truncate lowering: it completely hosed overScott Michel2008-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61447 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2008-12-09
| | | | | | | | - Fix call.ll and call_indirect.ll expected results, now that it's using a different pre-register allocation scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60741 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU: Add new directory under tests/CodeGen/CellSPU to retain tests thatScott Michel2008-12-05
| | | | | | | | | | | | | | aren't part of the test suite but are generally useful nonetheless, and can be expanded later to test the backend against the actual Cell SPU system. There's basically no other good place to put this code, so put it here for the time being. - vecoperations.c: Vector shuffles for all supported vector types, tests for v16i8 add and multiply. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60566 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some tests. The grep for "il" was matching "file".Rafael Espindola2008-12-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60485 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2008-12-02
| | | | | | | | | | | - Incorporate Tilmann Scheller's ISD::TRUNCATE custom lowering patch - Update SPU calling convention info, even if it's not used yet (but can be at some point or another) - Ensure that any-extended f32 loads are custom lowered, especially when they're promoted for use in printf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60438 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2008-12-01
| | | | | | | | | | - Fix v2[if]64 vector insertion code before IBM files a bug report. - Ensure that zero (0) offsets relative to $sp don't trip an assert (add $sp, 0 gets legalized to $sp alone, tripping an assert) - Shuffle masks passed to SPUISD::SHUFB are now v16i8 or v4i32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60358 91177308-0d34-0410-b5e6-96231b3b80d8
* APIntify a test which is potentially unsafe otherwise, and fix the Eli Friedman2008-11-30
| | | | | | | | | | | nearby FIXME. I'm not sure what the right way to fix the Cell test was; if the approach I used isn't okay, please let me know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60277 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2008-11-25
| | | | | | | | | | (a) Remove conditionally removed code in SelectXAddr. Basically, hope for the best that the A-form and D-form address predicates catch everything before the code decides to emit a X-form address. (b) Expand vector store test cases to include the usual suspects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60034 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU: test should use shlqby, not shlqbyiScott Michel2008-11-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60001 91177308-0d34-0410-b5e6-96231b3b80d8
* XFAIL this test. A recent CellSPU check-in broke it.Bill Wendling2008-11-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60000 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2008-11-24
| | | | | | | | | | (a) Slight rethink on i64 zero/sign/any extend code - use a shuffle to directly zero-extend i32 to i64, but use rotates and shifts for sign extension. Also ensure unified register consistency. (b) Add new test harness for i64 operations: i64ops.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59970 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2008-11-24
| | | | | | | | | | | (a) Improve the extract element code: there's no need to do gymnastics with rotates into the preferred slot if a shuffle will do the same thing. (b) Rename a couple of SPUISD pseudo-instructions for readability and better semantic correspondence. (c) Fix i64 sign/any/zero extension lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59965 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was itScott Michel2008-11-22
| | | | | | | ever conceived to occur). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59891 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2008-11-21
| | | | | | | | | (a) Fix bgs 3052, 3057 (b) Incorporate Duncan's suggestions re: i1 promotion (c) Indentation updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59790 91177308-0d34-0410-b5e6-96231b3b80d8
* Un-XFAIL tests now that they're fixed.Bill Wendling2008-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59023 91177308-0d34-0410-b5e6-96231b3b80d8
* r59009 broke these tests. XFAIL for now.Bill Wendling2008-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59010 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU: Update expected counts on expected patternsScott Michel2008-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58927 91177308-0d34-0410-b5e6-96231b3b80d8
* Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stackScott Michel2008-10-30
| | | | | | | | | | so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU. N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is still unexorcised code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58415 91177308-0d34-0410-b5e6-96231b3b80d8
* remove an xfailed test.Chris Lattner2008-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57695 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTRBill Wendling2008-08-31
| | | | | | | | | instructions in CellSPU as "Expand" so that they won't be generated. I added a "FIXME" so that this hack can be addressed and reverted once ISD::ROTR is supported in the .td files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55582 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAGBill Wendling2008-08-31
| | | | | | | | | combiner can now generate ROTR if the backend says that it can handle it. Cell SPU says this, but gets an error from code gen saying that it can't select ROTR. I'm xfailing this test until this can be fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55579 91177308-0d34-0410-b5e6-96231b3b80d8
* Add necessary 64-bit support so that gcc frontend compiles (mostly). CurrentScott Michel2008-06-02
| | | | | | | | issue is operand promotion for setcc/select... but looks like the fundamental stuff is implemented for CellSPU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51884 91177308-0d34-0410-b5e6-96231b3b80d8
* sabre brings to my attention that the 'tr' suffix is also obsoleteGabor Greif2008-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51349 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the last test with .llx extension to .ll, resolve duplicate test by ↵Gabor Greif2008-05-20
| | | | | | renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51328 91177308-0d34-0410-b5e6-96231b3b80d8
* Update and_ops.ll according to the recent dagcombiner changes.Dan Gohman2008-04-28
| | | | | | | | | Add a new test, and_ops_more.ll, which is XFAIL'd, to record the parts of and_ops.ll that were affected by this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50379 91177308-0d34-0410-b5e6-96231b3b80d8
* Upgrade these tests for the current intrinsic prototypes.Dan Gohman2008-04-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49669 91177308-0d34-0410-b5e6-96231b3b80d8
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