index
:
llvm
embtk-support-master
embtk-support-release-3.2
embtk-support-release-3.3
embtk-support-release-3.4
master
release-3.2
release-3.4
Unofficial llvm GIT mirror used in EmbToolkit
Git daemon user
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
test
/
CodeGen
/
R600
Commit message (
Expand
)
Author
Age
*
R600: Add failing control flow tests.
Matt Arsenault
2014-03-01
*
R600/SI: Expand all v16[if]32 operations
Tom Stellard
2014-02-28
*
R600/SI: Optimize SI_KILL for constant operands
Michel Danzer
2014-02-27
*
R600/SI: Allow SI_KILL for geometry shaders
Michel Danzer
2014-02-27
*
R600/SI: Custom select 64-bit ADD
Tom Stellard
2014-02-25
*
R600/SI - Add new CI arithmetic instructions.
Matt Arsenault
2014-02-24
*
[CodeGenPrepare] Fix the check of the legality of an instruction.
Quentin Colombet
2014-02-22
*
Fix more broken CHECK lines
Nico Rieck
2014-02-16
*
[CodeGenPrepare][AddressingModeMatcher] Give up on type promotion if the
Quentin Colombet
2014-02-14
*
TargetLowering: n * r where n > 2 should be an illegal addressing mode
Tom Stellard
2014-02-14
*
R600/SI: Expand all v8[if]32 operations
Tom Stellard
2014-02-13
*
R600/SI: Add a pattern for i32 anyext
Tom Stellard
2014-02-13
*
R600/SI: Completely Disable TypeRewriter on compute
Tom Stellard
2014-02-13
*
R600/SI: Split global vector loads with more than 4 elements
Tom Stellard
2014-02-13
*
R600/SI: Add ShaderType attribute to some tests
Tom Stellard
2014-02-13
*
R600/SI: Fix assertion on infinite loops.
Matt Arsenault
2014-02-11
*
R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used
Tom Stellard
2014-02-10
*
R600/SI: Add failing test for 3 x i64 vectors.
Matt Arsenault
2014-02-07
*
R600/SI: Add a MUBUF store pattern for Reg+Imm offsets
Tom Stellard
2014-02-06
*
R600/SI: Add a MUBUF store pattern for Imm offsets
Tom Stellard
2014-02-06
*
R600/SI: Add a MUBUF load pattern for Reg+Imm offsets
Tom Stellard
2014-02-06
*
R600/SI: Use immediates offsets for SMRD instructions whenever possible
Tom Stellard
2014-02-06
*
R600/SI: Add pattern for zero-extending i1 to i32
Michel Danzer
2014-02-05
*
R600/SI: Custom lower i64 ISD::SELECT
Tom Stellard
2014-02-04
*
R600: Enable vector fpow.
Tom Stellard
2014-02-04
*
R600/SI: Fix fneg for 0.0
Michel Danzer
2014-02-04
*
Add some xfailed R600 tests for 64-bit private accesses.
Matt Arsenault
2014-02-02
*
R600/SI: Fix insertelement with dynamic indices.
Matt Arsenault
2014-02-02
*
R600/SI: Add pattern for truncating i32 to i1
Michel Danzer
2014-01-28
*
R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
Michel Danzer
2014-01-27
*
R600/SI: Add intrinsic for S_SENDMSG instruction
Michel Danzer
2014-01-27
*
R600: Disable the BFE pattern
Tom Stellard
2014-01-23
*
R600: Correctly handle vertex fetch clauses the precede ENDIFs
Tom Stellard
2014-01-23
*
R600: Unconditionally unroll loops that contain GEPs with alloca pointers
Tom Stellard
2014-01-23
*
R600: Recommit 199842: Add work-around for the CF stack entry HW bug
Tom Stellard
2014-01-23
*
Revert "R600: Add work-around for the CF stack entry HW bug"
Tom Stellard
2014-01-22
*
R600: Add work-around for the CF stack entry HW bug
Tom Stellard
2014-01-22
*
R600: Refactor stack size calculation
Tom Stellard
2014-01-22
*
R600: MOVA is vector only
Tom Stellard
2014-01-22
*
R600: Take alignment into account when calculating the stack offset
Tom Stellard
2014-01-22
*
R600: Add support for global addresses with constant initializers
Tom Stellard
2014-01-22
*
R600: Begin private memory at the second GPR.
Tom Stellard
2014-01-22
*
R600/SI: Add support for i8 and i16 private loads/stores
Tom Stellard
2014-01-22
*
Fix broken CHECK lines.
Benjamin Kramer
2014-01-11
*
R600: Allow ftrunc
Tom Stellard
2013-12-20
*
Add REQUIRES:asserts to 3 tests in llvm/test/CodeGen/R600 added in r192212.
NAKAMURA Takumi
2013-12-19
*
R600/SI: Make private pointers be 32-bit.
Matt Arsenault
2013-12-19
*
R600/SI: Minor improvements to test.
Matt Arsenault
2013-12-14
*
R600/SI: Add i64 cmp tests
Matt Arsenault
2013-12-10
*
R600: Fix an infinite loop when trying to reorganize export/tex vector input
Vincent Lejeune
2013-12-10
[next]