llvm - Unofficial llvm GIT mirror used in EmbToolkit

	Commit message (Expand)	Author	Age
*	R600: Add SI load support for v[24]i32 and store for v2i32	Tom Stellard	2013-06-15
*	R600: Use correct encoding for Vertex Fetch instructions on Cayman	Tom Stellard	2013-06-14
*	R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman	Tom Stellard	2013-06-14
*	R600: Anti dep better handled in tex clause	Vincent Lejeune	2013-06-07
*	R600: Fix calculation of stack offset in AMDGPUFrameLowering	Tom Stellard	2013-06-07
*	R600: Fix the fetch limits for R600 generation GPUs	Tom Stellard	2013-06-07
*	R600: Add a pass that merge Vector Register	Vincent Lejeune	2013-06-05
*	R600: Schedule copy from phys register at beginning of block	Vincent Lejeune	2013-06-05
*	R600: Make sure to schedule AR register uses and defs in the same clause	Tom Stellard	2013-06-05
*	Revert "R600: Add a pass that merge Vector Register"	Rafael Espindola	2013-06-05
*	R600: Add a pass that merge Vector Register	Vincent Lejeune	2013-06-04
*	R600: Const/Neg/Abs can be folded to dot4	Vincent Lejeune	2013-06-04
*	R600: Swizzle texture/export instructions	Vincent Lejeune	2013-06-04
*	R600: Add a test for r183108	Vincent Lejeune	2013-06-04
*	R600/SI: Add support for work item and work group intrinsics	Tom Stellard	2013-06-03
*	R600/SI: Add a calling convention for compute shaders	Tom Stellard	2013-06-03
*	R600/SI: Custom lower i64 sign_extend	Tom Stellard	2013-06-03
*	R600/SI: Add support for global loads	Tom Stellard	2013-06-03
*	R600: use capital letter for PV channel	Vincent Lejeune	2013-06-03
*	R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg	Tom Stellard	2013-05-23
*	R600: Fix rotr.ll on non-asserts builds	Tom Stellard	2013-05-20
*	R600/SI: Add pattern for rotr	Tom Stellard	2013-05-20
*	R600: Swap the legality of rotl and rotr	Tom Stellard	2013-05-20
*	R600/SI: Add patterns for 64-bit shift operations	Tom Stellard	2013-05-20
*	R600: Lower int_load_input to copyFromReg instead of Register node	Vincent Lejeune	2013-05-17
*	R600: Use bottom up scheduling algorithm	Vincent Lejeune	2013-05-17
*	R600: Use depth first scheduling algorithm	Vincent Lejeune	2013-05-17
*	R600: Relax some vector constraints on Dot4.	Vincent Lejeune	2013-05-17
*	R600: Improve texture handling	Vincent Lejeune	2013-05-17
*	R600: Rename 128 bit registers.	Vincent Lejeune	2013-05-17
*	R600: Fix encoding for R600 family GPUs	Tom Stellard	2013-05-17
*	R600/SI: Add lit test coverage for the remaining patterns added recently	Michel Danzer	2013-05-14
*	R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ...	Tom Stellard	2013-05-10
*	R600: Expand SUB for v2i32/v4i32	Tom Stellard	2013-05-10
*	R600: Expand MUL for v4i32/v2i32	Tom Stellard	2013-05-10
*	R600: Expand SRA for v4i32/v2i32	Tom Stellard	2013-05-10
*	R600: Expand vselect for v4i32 and v2i32	Tom Stellard	2013-05-10
*	R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsics	Michel Danzer	2013-05-08
*	R600: Emit config values in register / value pairs	Tom Stellard	2013-05-06
*	R600: Stop emitting the instruction type byte before each instruction	Tom Stellard	2013-05-06
*	R600: Emit ISA for CALL_FS_* instructions	Tom Stellard	2013-05-06
*	R600: Expand vector or, shl, srl, and xor nodes	Tom Stellard	2013-05-03
*	R600: Add pattern for SHA-256 Ma function	Tom Stellard	2013-05-03
*	R600: Signed literals are 64bits wide	Vincent Lejeune	2013-05-02
*	R600: If previous bundle is dot4, PV valid chan is always X	Vincent Lejeune	2013-05-02
*	R600: Add a test to check that use_kill is emitted	Vincent Lejeune	2013-05-02
*	R600: Prettier asmPrint of Alu	Vincent Lejeune	2013-05-02
*	TBAA: remove !tbaa from testing cases if not used.	Manman Ren	2013-04-30
*	R600: fix loop-address.ll test	Vincent Lejeune	2013-04-30
*	R600: use native for alu	Vincent Lejeune	2013-04-30