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* Fix a typo, in a comment, in a test.Nick Lewycky2013-10-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192632 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert part of a fix from 2010, changes since then:Eric Christopher2013-10-14
| | | | | | | | | | | | a) x86-64 TLS has been documented b) the code path should use movq for the correct relocation to be generated. I've also added a fixme for the test case that we should improve the code generated, it should look something like is documented in the tls abi document. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192631 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineSink: Fix and tweak critical-edge breaking heuristic.Will Dietz2013-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per original comment, the intention of this loop is to go ahead and break the critical edge (in order to sink this instruction) if there's reason to believe doing so might "unblock" the sinking of additional instructions that define registers used by this one. The idea is that if we have a few instructions to sink "together" breaking the edge might be worthwhile. This commit makes a few small changes to help better realize this goal: First, modify the loop to ignore registers defined by this instruction. We don't sink definitions of physical registers, and sinking an SSA definition isn't going to unblock an upstream instruction. Second, ignore uses of physical registers. Instructions that define physical registers are rejected for sinking, and so moving this one won't enable moving any defining instructions. As an added bonus, while virtual register use-def chains are generally small due to SSA goodness, iteration over the uses and definitions (used by hasOneNonDBGUse) for physical registers like EFLAGS can be rather expensive in practice. (This is the original reason for looking at this) Finally, to keep things simple continue to only consider this trick for registers that have a single use (via hasOneNonDBGUse), but to avoid spuriously breaking critical edges only do so if the definition resides in the same MBB and therefore this one directly blocks it from being sunk as well. If sinking them together is meant to be, let the iterative nature of this pass sink the definition into this block first. Update tests to accomodate this change, add new testcase where sinking avoids pipeline stalls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192608 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar integer compare instructions.Chad Rosier2013-10-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Cortex-A57 supportBernard Ogden2013-10-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192591 91177308-0d34-0410-b5e6-96231b3b80d8
* Add subtarget feature support for Cortex-A53Bernard Ogden2013-10-14
| | | | | | | Some previous implicit defaults have changed, for example FP and NEON are now on by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192590 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in dynamic allocation memory on stack.Elena Demikhovsky2013-10-14
| | | | | | | | | The alignment of allocated space was wrong, see Bugzila 17345. Done by Zvi Rackover <zvi.rackover@intel.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192573 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: improve dump of S_WAITCNTVincent Lejeune2013-10-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192557 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use masked read sel for texture instructionsVincent Lejeune2013-10-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192554 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: fix swizzle exportVincent Lejeune2013-10-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192553 91177308-0d34-0410-b5e6-96231b3b80d8
* Force a CPU on test so it doesn't depend on microarchitectural scheduling ↵Benjamin Kramer2013-10-12
| | | | | | decisions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192532 91177308-0d34-0410-b5e6-96231b3b80d8
* For Mips16, start to consolidate all forms of 32 bit literal loading so thatReed Kotler2013-10-12
| | | | | | | | they can be better handled and optimized in the Mips16 constant island code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192520 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add scalar i32 add testMatt Arsenault2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192501 91177308-0d34-0410-b5e6-96231b3b80d8
* Use CHECK-LABELMatt Arsenault2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192500 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove kill flags after if conversion if necessaryMatthias Braun2013-10-11
| | | | | | | | | | | | | | | | | | | When if converting something like: true: ... = R0<kill> false: ... = R0<kill> then the instructions of the true block must not have a <kill> flag anymore, as the instruction of the false block follow and do still read the R0 value. Specifically this patch determines the set of register live-in in the false block (possibly after simulating the liveness changes of the duplicated instructions). Each of these live-in registers mustn't be killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192482 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Load slicing test case: attempt to really fix the buildbots ↵Quentin Colombet2013-10-11
| | | | | | | | | (used sse4.2 instead of avx!). <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192480 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set ↵Quentin Colombet2013-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sse4.2 support. This should fix the buildbots. Original commit message: [DAGCombiner] Slice a big load in two loads when the element are next to each other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192476 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails ↵Quentin Colombet2013-10-11
| | | | | | on ubuntu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192474 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Tests: Be less dependent on a specific schedule/regalloc"Matthias Braun2013-10-11
| | | | | | | | | This reverts r192454 Apparently FileCheck isn't as smart as I though and does not enforce a topological order between variable defs+uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192472 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Slice a big load in two loads when the element are next to eachQuentin Colombet2013-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix FP ABI attributes with no VFP enabled.Amara Emerson2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192458 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests: Be less dependent on a specific schedule/regallocMatthias Braun2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192454 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Improves robustness of the test by enhancing pattern matching.Matheus Almeida2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192446 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Switch from StrongPHIElimination to PHIElimination in ↵Justin Holewinski2013-10-11
| | | | | | | | NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc Fixes PR17529 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192445 91177308-0d34-0410-b5e6-96231b3b80d8
* Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom ↵Justin Holewinski2013-10-11
| | | | | | | | | | | | | comments for implicit defs For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers, while NVPTX uses virtual registers (with a couple of exceptions). Now, the implicit def comment will be emitted as a true PTX register name. Other targets can use this to customize the output of implicit def comments. Fixes PR17519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192444 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Add a test case for disabled neon/fpu features.Amara Emerson2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192440 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from ↵Daniel Sanders2013-10-11
| | | | | | normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-11
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target fix bug in emitArrayBound() causing segmentation faultRobert Lytton2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192434 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target does not emit '.hidden' or '.protected' attributesRobert Lytton2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192433 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: fix bug in XCoreLowerThreadLocal.cppRobert Lytton2013-10-11
| | | | | | | | | When a ConstantExpr which uses a thread local is part of a PHI node instruction, the insruction that replaces the ConstantExpr must be inserted in the predecessor block, in front of the terminator instruction. If the predecessor block has multiple successors, the edge is first split. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192432 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: add XCoreTargetLowering::isZExtFree()Robert Lytton2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192431 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-11
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] ↵Daniel Sanders2013-10-11
| | | | | | from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction set AdvSIMD (copy).Kevin Qin2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests: Do not unnecessarily depend on kill commentsMatthias Braun2013-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192404 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests: Use CHECK-LABEL where possibleMatthias Braun2013-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192403 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192375 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-10
| | | | | | | | | | | We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-10
| | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-10
| | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-10
| | | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable function padding to get this test to pass on atom.Benjamin Kramer2013-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192348 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-10
| | | | | | | | | | | | | | | | | | | | | | When we had a sequence like: s1 = VLDRS [r0, 1], Q0<imp-def> s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def> s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def> s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def> we were gathering the {s0, s1} loads below the s3 load. This is fine, but confused the verifier since now the s3 load had Q0<imp-use> with no definition above it. This should mark such uses <undef> as well. The liveness structure at the beginning and end of the block is unaffected, and the true sN definitions should prevent any dodgy reorderings being introduced elsewhere. rdar://problem/15124449 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192344 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Do not generate INS/EXT nodes if target does not have support forAkira Hatanaka2013-10-09
| | | | | | | | ins/ext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192330 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Disable tail call optimization for sparc64.Venkatraman Govindaraju2013-10-09
| | | | | | | | This patch fixes PR17506. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192294 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: enable MISched by default.Tim Northover2013-10-09
| | | | | | | | | | | | Substantial SelectionDAG scheduling is going away soon, and is interfering with Hao's attempts to implement LDn/STn instructions, so I say we make the leap first. There were a few reorderings (inevitably) which broke some tests. I tried to replace them with CHECK-DAG variants mostly, but some too complex for that to be useful and I just reordered them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192282 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: migrate ADRP relaxation test to be llvm-mc only.Tim Northover2013-10-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192281 91177308-0d34-0410-b5e6-96231b3b80d8
* Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. ↵Craig Topper2013-10-09
| | | | | | This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192266 91177308-0d34-0410-b5e6-96231b3b80d8
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