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* Added parsing co-processor names starting with "cr"Renato Golin2014-06-26
| | | | | | | | | | Additional compliant GAS names for coprocessor register name are enabled for all instruction with parameter MCK_CoprocReg: LDC,LDC2,STC,STC2,CDP,CDP2,MCR,MCR2,MCRR,MCRR2,MRC,MRC2,MRRC,MRRC2 Patch by Andrey Kuharev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211776 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: mark UBFX as not allowing PC.Tim Northover2014-06-23
| | | | | | | | | Strictly, it's unpredictable. But we don't quite model that yet and an error is better than ignoring the issue. This one somehow got left out before though. rdar://problem/15997748 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211490 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: adjust text section flags for WoASaleem Abdulrasool2014-06-22
| | | | | | | | | | | | | | | | | | | | | | | Correct the section flags for code built for Windows on ARM with `-ffunction-sections`. Windows on ARM uses solely Thumb-2 instructions, and indicates that the function is thumb by placing it in a text section that has IMAGE_SCN_MEM_16BIT flag set. When we encounter a .section directive, a new section is constructed. This may be a text segment. In order to identify that we need the additional flag, expose the target triple through the ObjectFileInfo as this information is lost otherwise. Since any modern ARM targeting environment on Windows would be Thumb-2 (Windows ARM NT or Windows Embedded Compact), introducing a new flag to indicate the section attribute seems to be a bit overkill. Simply depend on the target triple. Since there is one location that this information is currently needed, creating a target specific assembly parser and delegating the parsing of section switches also feels a bit heavy handed. If it turns out that this information ends up changing additional behaviour, then it may be worth considering that alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211481 91177308-0d34-0410-b5e6-96231b3b80d8
* Since we're using DW_AT_string rather than DW_AT_strp for debug_infoEric Christopher2014-06-19
| | | | | | | | for assembly files we can't depend on the offset within the section after a string since it could be different between producers etc. Relax these tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211308 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests for r211273Oliver Stannard2014-06-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211279 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-09
| | | | | | We can just split targets_to_build in one place and make it immutable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210496 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: fix text section characteristics for WoASaleem Abdulrasool2014-06-08
| | | | | | | | | | link.exe requires that the text section has the IMAGE_SCN_MEM_16BIT flag set. Otherwise, it will treat the function as ARM. If this occurs, then jumps to the function will fail, switching from thumb to ARM mode execution. With this change, it is possible to link using the MSVC linker as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210415 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Generalize some tests to handle variations in attribute ordering.David Blaikie2014-05-23
| | | | | | | | | | | | | | | | In an effort to fix inlined debug info in situations where the out of line definition of a function preceeds any inlined usage, the order in which some attributes are added to subprogram DIEs may change. (in essence, definition-necessary attributes like DW_AT_low_pc/high_pc will be added immediately, but the names, types, and other features will be delayed to module end where they may either be added to the subprogram DIE or instead reference an abstract definition for those values) These tests can be generalized to be resilient to this change. 5 or so tests actually have to be incompatibly changed to cope with this reordering and will go along with the change that affects the order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209554 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: correct IMAGE_REL_ARM_MOV32T relocation emissionSaleem Abdulrasool2014-05-21
| | | | | | | | | | | | This corrects the emission of IMAGE_REL_ARM_MOV32T relocations. Previously, we were avoiding the high portion of the relocation too early. If there was a section-relative relocation with an offset greater than 16-bits (65535), you would end up truncating the high order bits of the offset. Allow the current relocation representation to flow through out the MC layer to the object writer. Use the new ability to restrict recorded relocations to avoid emitting the relocation into the final object. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209337 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMEB: Additional test files for ARM fixupsChristian Pirker2014-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209200 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-14
| | | | | | | | | | | | | | The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208751 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Additional test files for thumb fixups (checked with llvm-mv ↵Christian Pirker2014-05-13
| | | | | | -show-encoding) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208712 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Additional test files for thumb fixupsChristian Pirker2014-05-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208691 91177308-0d34-0410-b5e6-96231b3b80d8
* test: fix silly typoSaleem Abdulrasool2014-05-08
| | | | | | Oh silly Darwin and your case insensitive file system. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208274 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: support FK_SecRel_2 relocations on WoASaleem Abdulrasool2014-05-08
| | | | | | | | This adds FK_SecRel_2 relocation support to ARM. This enables the building of object files for armv7-windows-msvc which enables CodeView line tables for debugging as opposed to armv7-windows-itanium which currently uses DWARF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208273 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: For thumb fixups store halfwords high first and low secondChristian Pirker2014-05-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208076 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix spelling.Joerg Sonnenberger2014-05-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207982 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: support FK_SecRel_4 for Windows on ARMSaleem Abdulrasool2014-05-04
| | | | | | | | | Add handling for FK_SecRel_4 (4-byte section relative relocations). These are used by the generation of DWARF debug information (the abbrevations use section relative relocations). This will also be used in generation of CodeView line tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207941 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: place .file records into the correct sectionSaleem Abdulrasool2014-05-02
| | | | | | | | | .file records are supposed to have a section identifier of 65534 (IMAGE_SCN_DEBUG) rather than 0. This is spelt out clearly within the PE/COFF specification. Fix this minor oversight with the implementation for support for .file records. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207851 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't force symbols to be globals in .thumb_set.Rafael Espindola2014-05-01
| | | | | | | | | | | | | | | | | | | | | | We currently force symbols to be globals in .thumb_set. The intent seems to be that given .thumb_set foo, bar we emit an undefined symbol to bar if it is never defined. The side effect is that we mark bar as global, even if it is defined, which gas does not. Producing an undefined reference to bar is a general difference from MC and gas. For example, given a = b gas will produce an undefined reference to b, MC will not. I would be surprised if any code depends on this, but it it does, we should fix the general difference, not special case .thumb_set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207757 91177308-0d34-0410-b5e6-96231b3b80d8
* Correction to assert statemtent to allow 32-bit unsigned numbers with the ↵Richard Barton2014-05-01
| | | | | | | | | | top bit set. This fixes an ARM assembler crash - regression test added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207747 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: print COFF function header for Windows on ARMSaleem Abdulrasool2014-04-30
| | | | | | | | | Emit the COFF header when printing out the function. This is important as the header contains two important pieces of information: the storage class for the symbol and the symbol type information. This bit of information is required for the linker to correctly identify the type of symbol that it is dealing with. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207613 91177308-0d34-0410-b5e6-96231b3b80d8
* Parse and create GOT_PREL relocations.Joerg Sonnenberger2014-04-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207526 91177308-0d34-0410-b5e6-96231b3b80d8
* Centralize the handling of the thumb bit.Rafael Espindola2014-04-29
| | | | | | | | | | | | | This patch centralizes the handling of the thumb bit around MCStreamer::isThumbFunc and makes isThumbFunc handle aliases. This fixes a corner case, but the main advantage is having just one way to check if a MCSymbol is thumb or not. This should still be refactored to be ARM only, but at least now it is just one predicate that has to be refactored instead of 3 (isThumbFunc, ELF_Other_ThumbFunc, and SF_ThumbFunc). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207522 91177308-0d34-0410-b5e6-96231b3b80d8
* Add emitThumbSet to the arm target streamer.Rafael Espindola2014-04-27
| | | | | | | This fixes the asm printer implementation and lets the parser be unaware of what .thumb_set is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207381 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: duplicate .file test for WoA (SVN r207341)Saleem Abdulrasool2014-04-27
| | | | | | | Since the COFF tests are dependent on X86, duplicate the test for ARM. Use the default check prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207365 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: move ARM COFF test to ARM directorySaleem Abdulrasool2014-04-27
| | | | | | | The COFF tests all assume X86. Just move the new COFF tests under ARM to appease the build bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207346 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18921, "vmov" part.Stepan Dyatkovskiy2014-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | Added support for bytes replication feature, so it could be GAS compatible. E.g. instructions below: "vmov.i32 d0, 0xffffffff" "vmvn.i32 d0, 0xabababab" "vmov.i32 d0, 0xabababab" "vmov.i16 d0, 0xabab" are incorrect, but we could deal with such cases. For first one we should emit: "vmov.i8 d0, 0xff" For second one ("vmvn"): "vmov.i8 d0, 0x54" For last two instructions it should emit: "vmov.i8 d0, 0xab" P.S.: In ARMAsmParser.cpp I have also fixed few nearby style issues in old code. Just for keeping method bodies in harmony with themselves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207080 91177308-0d34-0410-b5e6-96231b3b80d8
* Follow aliases when determining if a symbol is thumb.Rafael Espindola2014-04-22
| | | | | | This fixes pr19484. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206917 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the ARM assembler to require a :lower16: or :upper16 on non-constantKevin Enderby2014-04-18
| | | | | | | | | | | | | | | | | | | | | | | expressions for mov instructions instead of silently truncating by default. For the ARM assembler, we want to avoid misleadingly allowing something like "mov r0, <symbol>" especially when we turn it into a movw and the expression <symbol> does not have a :lower16: or :upper16" as part of the expression. We don't want the behavior of silently truncating, which can be unexpected and lead to bugs that are difficult to find since this is an easy mistake to make. This does change the previous behavior of llvm but actually matches an older gnu assembler that would not allow this but print less useful errors of like “invalid constant (0x927c0) after fixup” and “unsupported relocation on symbol foo”. The error for llvm is "immediate expression for mov requires :lower16: or :upper16" with correct location information on the operand as shown in the added test cases. rdar://12342160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206669 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit - Added a new lineKonrad Anheim2014-04-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206399 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC] Emit an error if cfi_startproc is used before a symbol is defined.Quentin Colombet2014-04-15
| | | | | | | | | | Currently, we bind those directives with the last symbol, so if none has been defined, this would lead to a crash of the compiler. <rdar://problem/15939159> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206236 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't lose the thumb bit by using relocations with sections.Rafael Espindola2014-04-11
| | | | | | This fixes a regression from r205076. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206047 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the use of "%e" as it is not a valid expansion like "%t".Kaelyn Takata2014-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205991 91177308-0d34-0410-b5e6-96231b3b80d8
* For the ARM integrated assembler add checking of theKevin Enderby2014-04-10
| | | | | | | | | | | | | | | | | | | | alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205986 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "For the ARM integrated assembler add checking of the alignments on ↵Reid Kleckner2014-04-10
| | | | | | | | | | | | | vld/vst instructions. And report errors for alignments that are not supported." It doesn't build with MSVC 2012, because MSVC doesn't allow union members that have non-trivial default constructors. This change added 'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor non-trivial. This reverts commit r205930. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205944 91177308-0d34-0410-b5e6-96231b3b80d8
* For the ARM integrated assembler add checking of theKevin Enderby2014-04-09
| | | | | | | | | | | | | | | | alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. rdar://11312406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205930 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2014-04-08
| | | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld3.16 {d0[], d2[], d4[]}, [r4]! was being printed as: vld3.16 {d0[], d1[], d2[]}, [r4]! rdar://16531387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205779 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18921 (LDRD/STRD part)::Stepan Dyatkovskiy2014-04-04
| | | | | | | | | Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now. Added new tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205622 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed register class in STRD instruction for Thumb2 mode.Stepan Dyatkovskiy2014-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205612 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: update even more testsSaleem Abdulrasool2014-04-03
| | | | | | | | | More updating of tests to be explicit about the target triple rather than relying on the default target triple supporting ARM mode. Indicate to lit that object emission is not yet available for Windows on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205545 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fixup more tests to specify the target more explicitlySaleem Abdulrasool2014-04-03
| | | | | | | | | | | | | This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
* PR19320:Stepan Dyatkovskiy2014-04-03
| | | | | | | | | The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommitted fix for PR18931, with extended tests set.Stepan Dyatkovskiy2014-03-29
| | | | | | | | | | | | | | | Issue subject: Crash using integrated assembler with immediate arithmetic Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205094 91177308-0d34-0410-b5e6-96231b3b80d8
* Completely rewrite ELFObjectWriter::RecordRelocation.Rafael Espindola2014-03-29
| | | | | | | | | | | | | | | | | | | I started trying to fix a small issue, but this code has seen a small fix too many. The old code was fairly convoluted. Some of the issues it had: * It failed to check if a symbol difference was in the some section when converting a relocation to pcrel. * It failed to check if the relocation was already pcrel. * The pcrel value computation was wrong in some cases (relocation-pc.s) * It was missing quiet a few cases where it should not convert symbol relocations to section relocations, leaving the backends to patch it up. * It would not propagate the fact that it had changed a relocation to pcrel, requiring a quiet nasty work around in ARM. * It was missing comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205076 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-28
| | | | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205007 91177308-0d34-0410-b5e6-96231b3b80d8
* Rejected r204899 and r204900 due to remaining test failures on ↵Stepan Dyatkovskiy2014-03-27
| | | | | | cmake-llvm-x86_64-linux buildbot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204901 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed test for r204899 (pr18931 fix)Stepan Dyatkovskiy2014-03-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204900 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for pr18931: Crash using integrated assembler with immediate arithmeticStepan Dyatkovskiy2014-03-27
| | | | | | | | | | | | | Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204899 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: raise error message when complex SO expressions can't really beJiangning Liu2014-03-27
| | | | | | | solved as a constant at compilation time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204898 91177308-0d34-0410-b5e6-96231b3b80d8
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