summaryrefslogtreecommitdiff
path: root/test/MC/Disassembler
Commit message (Expand)AuthorAge
* [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinterBradley Smith2014-04-25
* [ARM64] Support crc predicate on ARM64.Kevin Qin2014-04-25
* AArch64: print NEON lists with a space.Tim Northover2014-04-24
* X86Disassembler - fixed a bug in immediate printElena Demikhovsky2014-04-23
* [ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin2014-04-23
* [X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.Craig Topper2014-04-17
* [ARM64] Change SYS without a register to an alias to make disassembling more ...Bradley Smith2014-04-09
* [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.Bradley Smith2014-04-09
* [ARM64] Properly support both apple and standard syntax for FMOVBradley Smith2014-04-09
* [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.Bradley Smith2014-04-09
* [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.Bradley Smith2014-04-09
* [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.Bradley Smith2014-04-09
* [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ...Bradley Smith2014-04-09
* [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.Bradley Smith2014-04-09
* [ARM64] Rename LR to the UAL-compliant 'X30'.Bradley Smith2014-04-09
* [ARM64] Rename FP to the UAL-compliant 'X29'.Bradley Smith2014-04-09
* [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ...Bradley Smith2014-04-09
* [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.Bradley Smith2014-04-09
* [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have t...Bradley Smith2014-04-09
* [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.Bradley Smith2014-04-09
* [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.Bradley Smith2014-04-09
* [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and ...Bradley Smith2014-04-09
* [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembl...Bradley Smith2014-04-09
* [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to u...Bradley Smith2014-04-09
* [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also...Bradley Smith2014-04-09
* [ARM64] STRHro and STRBro were not being decoded at all.Bradley Smith2014-04-09
* [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB i...Bradley Smith2014-04-09
* [ARM64] Register-offset loads and stores with the 'option' field equal to 00x...Bradley Smith2014-04-09
* ARM64: initial backend importTim Northover2014-03-29
* [SystemZ] Add support for z196 float<->unsigned conversionsRichard Sandiford2014-03-21
* Test case for r204305.Craig Topper2014-03-20
* [PowerPC] Initial support for the VSX instruction setHal Finkel2014-03-13
* [Sparc] Add support for decoding 'swap' instruction.Venkatraman Govindaraju2014-03-09
* This patch implements jalx instruction for Mips architecture.This instruction...Vladimir Medic2014-03-03
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-02
* [Sparc] Add support for decoding jmpl/retl/ret instruction.Venkatraman Govindaraju2014-03-02
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-02
* [Sparc] Add support to decode unimp instruction.Venkatraman Govindaraju2014-03-01
* [Sparc] Add support to decode negative simm13 operands in the sparc disassemb...Venkatraman Govindaraju2014-03-01
* [Sparc] Add support for decoding call instructions in the sparc disassembler.Venkatraman Govindaraju2014-03-01
* [Sparc] Add support to disassemble sparc memory instructions.Venkatraman Govindaraju2014-03-01
* [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the ...Venkatraman Govindaraju2014-03-01
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0x...Craig Topper2014-02-19
* Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 shoul...Craig Topper2014-02-17
* Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.Craig Topper2014-02-15
* [Sparc] Correct quad register list in the asm parser.Venkatraman Govindaraju2014-01-24
* [x86] Fix disassembly of MOV16ao16 et al.David Woodhouse2014-01-20
* [x86] Fix 16-bit disassembly of JCXZ/JECXZDavid Woodhouse2014-01-20
* [x86] Rename MOVSD/STOSD/LODSD/OUTSD to MOVSL/STOSL/LODSL/OUTSLDavid Woodhouse2014-01-20
* [x86] Fix disassembly of callw instructionDavid Woodhouse2014-01-20
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-14 06:50:11 +0000