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* ARM: add operands pre-writeback variants when neededAmaury de la Vieuville2013-06-18
* ARM: fix thumb literal loads decodingAmaury de la Vieuville2013-06-18
* ARM: thumb stores cannot use PC as dest registerAmaury de la Vieuville2013-06-18
* ARM: fix thumb coprocessor instruction with pre-writeback disassemblyAmaury de la Vieuville2013-06-14
* ARM: fix B decodingAmaury de la Vieuville2013-06-13
* This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ar...Mihai Popa2013-06-11
* ARM: Enforce decoding rules for VLDn instructionsAmaury de la Vieuville2013-06-11
* ARM: Fix STREX/LDREX reecodingAmaury de la Vieuville2013-06-11
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-10
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-08
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-08
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-08
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-08
* This is a simple patch that changes RRX and RRXS to accept all registers as o...Mihai Popa2013-06-05
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-31
* ARM: fix VEXT encoding corner caseTim Northover2013-05-31
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-29
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-28
* VSTn instructions have a number of encoding constraints which are not impleme...Mihai Popa2013-05-20
* Q registers are encoded in fields of the same length as D registers. As Q reg...Mihai Popa2013-05-20
* [SystemZ] Make use of SUBTRACT HALFWORDRichard Sandiford2013-05-15
* [SystemZ] Consolidate disassembler tests for valid input into 2 big testsRichard Sandiford2013-05-15
* [SystemZ] Add disassembler supportRichard Sandiford2013-05-14
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instruction...Mihai Popa2013-05-13
* [XCore] Add LDAPB instructions.Richard Osborne2013-05-05
* [XCore] Add BLRB instructions.Richard Osborne2013-05-05
* s tightens up the encoding description for ARM post-indexed ldr instructions....Mihai Popa2013-04-30
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-26
* ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover2013-04-19
* ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover2013-04-19
* [mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka2013-04-18
* Use object file specific section type for initial text sectionNico Rieck2013-04-14
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-12
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-11
* fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo2013-04-10
* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-10
* [XCore] Add bru instruction.Richard Osborne2013-04-04
* [XCore] The RRegs register class is a superset of GRRegs.Richard Osborne2013-04-04
* [XCore] Check disassembly of the st8 instruction.Richard Osborne2013-04-03
* [XCore] Update disassembler test to improve coverage of the instructions.Richard Osborne2013-04-03
* AArch64: implement ETMv4 trace system registers.Tim Northover2013-04-03
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when th...Gordon Keiser2013-03-28
* AArch64: implement GICv3 system registersTim Northover2013-03-28
* Patch by Gordon Keiser!Joe Abbey2013-03-26
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-25
* Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby2013-03-11
* AArch64: remove post-encoder method from FCMP (immediate) instructions.Tim Northover2013-02-28
* Make ARMAsmPrinter generate the correct alignment specifier syntax in instruc...Kristof Beyls2013-02-22
* [XCore] Add missing 2r instructions.Richard Osborne2013-02-17
* [XCore] Add TSETR instruction.Richard Osborne2013-02-17
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