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	Commit message (Collapse)	Author	Age
*	This patch fixes a bug in floating point operands parsing, when instruction ↵	Vladimir Medic	2013-11-13
\| \| \| \| \| \|	alias uses default register operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
*	This patch implements Mips load/store instructions from/to coprocessor 2. ↵	Vladimir Medic	2013-09-16
\| \| \| \| \| \|	Test cases are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of ↵	Vladimir Medic	2013-09-10
\| \| \| \| \| \|	register when PFU is 32 bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190397 91177308-0d34-0410-b5e6-96231b3b80d8
*	[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.	Akira Hatanaka	2013-08-28
\| \| \| \| \| \| \| \|	Also, fix predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
*	[mips] Fix instruction definitions that were incorrectly marked as ↵	Akira Hatanaka	2013-08-19
\| \| \| \| \| \|	code-gen-only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188690 91177308-0d34-0410-b5e6-96231b3b80d8
*	This patch implements parsing of mips FCC register operands. The example ↵	Vladimir Medic	2013-07-30
\| \| \| \| \| \|	instructions have been added to test files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
*	[mips] Fix MipsAsmParser::parseCCRRegs.	Akira Hatanaka	2013-07-22
\| \| \| \| \| \| \| \| \| \|	Enable parsing all 32 floating point control registers $0-31 and stop trying to parse floating point condition code register $fcc0. Also, return ParseFail if the operand being parsed is not in the expected format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186861 91177308-0d34-0410-b5e6-96231b3b80d8
*	This patch extends mips register parsing methods to allow indexed register ↵	Vladimir Medic	2013-07-18
\| \| \| \| \| \|	parsing. The corresponding test cases are added to the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186567 91177308-0d34-0410-b5e6-96231b3b80d8
*	Mips assembler: Explicit floating point condition register recognition.	Jack Carter	2013-04-15
\| \| \| \| \| \| \| \| \| \| \| \| \|	This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
*	Use object file specific section type for initial text section	Nico Rieck	2013-04-14
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
*	Adding support for instructions mfc0, mfc2, mtc0, mtc2	Jack Carter	2012-10-06
\| \| \| \| \| \| \| \| \|	move from and to coprocessors 0 and 2. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
*	The Mips standalone assembler fpu instruction support.	Jack Carter	2012-09-07
	Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163363 91177308-0d34-0410-b5e6-96231b3b80d8