summaryrefslogtreecommitdiff
path: root/test/MC
Commit message (Collapse)AuthorAge
* [mips] Add explicit N32 and N64 tests to nabi-regs.s testDaniel Sanders2014-02-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201684 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-19
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-19
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
* MCAsmParser: support required parametersSaleem Abdulrasool2014-02-19
| | | | | | | | | | | This enhances the macro parser to parse and handle parameter qualifications, which is needed to support required formal parameters in macro definitions. A required parameter may not be defaulted (though providing a default value is accepted with a warning). This improves GAS compatibility. Partially addresses PR9248. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201630 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the arm assembler so that this malformed instruction:Kevin Enderby2014-02-17
| | | | | | | | | | | | | | | | | | | ldrd r6, r7 [r2, #15] simply gives an error and does not triggers an assertion. As Jim points out, the diagnostic is really strange here, but fixing that would be more complicated. The missing comma results in the parser expecting a construct like r2[2], which is the vector index thing the error message is talking about. That's not what the user intended, though, and there's nothing else in the instruction that looks at all like a vector. Yet more fallout from not having a real parser here and trying to do context-free generic matching for addressing modes. rdar://15097243 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201531 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for assigning to . in AsmParser.Anders Waldenborg2014-02-17
| | | | | | | | | | | This is implemented by handling assignments to the '.' pseudo symbol as ".org" directives. Differential Revision: http://llvm-reviews.chandlerc.com/D2625 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201530 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 ↵Craig Topper2014-02-17
| | | | | | should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201507 91177308-0d34-0410-b5e6-96231b3b80d8
* MCAsmParser: add some mixed argument testsSaleem Abdulrasool2014-02-17
| | | | | | | Add some tests to explicitly validate handling of comma and non-comma separated arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201500 91177308-0d34-0410-b5e6-96231b3b80d8
* MCAsmParser: better handling for named argumentsSaleem Abdulrasool2014-02-17
| | | | | | | | | | | | | | | | | | | Until this point only macro definition with named parameters were parsed but the names were ignored. This adds support for using that information for named parameter instantiation. In order to support the full semantics of the keyword arguments, the arguments are no longer lazily initialised since the keyword arguments can be specified out of order and partially if they are defaulted. Prepopulate the arguments with the default value for any defaulted parameters, and then parse the specified arguments. This simplies some of the handling of the arguments in the inner loop since empty arguments simply increment the parameter index and move on. Note that keyword and positional arguments cannot be mixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201499 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix broken CHECK linesNico Rieck2014-02-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201479 91177308-0d34-0410-b5e6-96231b3b80d8
* MCAsmParser: relax declaration parsingSaleem Abdulrasool2014-02-16
| | | | | | | | The Linux kernel defines empty macros for compatibility with ARM UAL syntax. The comma after the name is optional, and if present can be safely lexed. This improves compatibility with the GNU assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201474 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: (partially) support .arch_extension directiveSaleem Abdulrasool2014-02-16
| | | | | | | | | | | | This adds a partial implementation of the .arch_extension directive to the integrated ARM assembler. There are a number of limitations to this implementation arising from the target backend support rather than the implementation itself. Namely, iWMMXT (v1 and v2), Maverick, and XScale support is not present in the ARM backend. Currently, there is no check for A-class only (needed for virt), and no ARMv6k detection (needed for os and sec). The remainder of the extensions are fully supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201471 91177308-0d34-0410-b5e6-96231b3b80d8
* Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.Craig Topper2014-02-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201463 91177308-0d34-0410-b5e6-96231b3b80d8
* Support DWARF discriminators in object streamer.Diego Novillo2014-02-14
| | | | | | | | | | | | | | | Summary: This adds support for emitting DWARF path discriminator values in the object streamer. It also changes the DWARF dumper to show discriminator values in the line table output. Reviewers: echristo CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2794 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201427 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify checks in MC/AsmParser/directive_loc.sDiego Novillo2014-02-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201361 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix generation of 'isa' and 'discriminator' keywords.Diego Novillo2014-02-13
| | | | | | | | | | | | | | | | | Summary: There should be a space before each of these two keywords to avoid generating invalid assembly files. NOTE: I could not find an obvious maintainers in CODE_OWNERS.TXT, but this seems related to debug info. Reviewers: echristo CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2791 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201359 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a bit. Formatting only.Jim Grosbach2014-02-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201174 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Thumb2 LDR(literal) can target SP.Jim Grosbach2014-02-11
| | | | | | | | | Fix a slightly overzealous destination register restriction for the 'without .w' alias. Add some explicit testcases. rdar://16033140 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201173 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Optimized BUILD_VECTOR pattern; Elena Demikhovsky2014-02-11
| | | | | | | fixed encoding of VEXTRACTPS instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201134 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Handle aliases of conditional branches without b.pred form.Chad Rosier2014-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201091 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Add DLSA instruction.Matheus Almeida2014-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201081 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-10
| | | | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201065 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmParser: Parse (and ignore) nested .macro definitions.Benjamin Kramer2014-02-09
| | | | | | | | | This enables a slightly odd feature of gas. The macro is defined when the outermost macro is instantiated. PR18599 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201045 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: change attribute tests to use parsed formSaleem Abdulrasool2014-02-08
| | | | | | | | | This makes the tests more readable by using the -arm-attributes decoding support in llvm-readobj since that is now available. Change the invocation commands to be similar to other test and use a more precise triple (the tests only require ARM EABI support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201029 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove -arm-disable-ehabi optionRenato Golin2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200988 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed comment.Sasa Stankovic2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200969 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing synthetic instruction 'mov'. Venkatraman Govindaraju2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200965 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Emit correct encoding for atomic instructions. Also, add support for ↵Venkatraman Govindaraju2014-02-07
| | | | | | parsing CAS instructions to test the CAS encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200963 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the X86 assembler for .intel_syntax to acceptKevin Enderby2014-02-06
| | | | | | | | | the << and >> bitwise operators. rdar://15975725 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200896 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Resolve thumb_bl fixup in same MCFragment.Logan Chien2014-02-05
| | | | | | | | | | | | | | | In Thumb1 mode, bl instruction might be selected for branches between basic blocks in the function if the offset is greater than 2KB. However, this might cause SEGV because the destination symbol is not marked as thumb function and the execution mode will be reset to ARM mode. Since we are sure that these symbols are in the same data fragment, we can simply resolve these local symbols, and don't emit any relocation information for this bl instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200842 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed a bug in EVEX encoding (the bug appeared after r200624)Elena Demikhovsky2014-02-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200837 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Implement %hi(sym1 - sym2) and %lo(sym1 - sym2) expressionsPetar Jovanovic2014-02-04
| | | | | | | | | | | | Patch implements %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions for MIPS by creating target expression class MipsMCExpr. Patch by Sasa Stankovic. Differential Revision: http://llvm-reviews.chandlerc.com/D2592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200783 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Fix .octa output for APInts with BitWidth > 128David Woodhouse2014-02-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200615 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add support for .octaDavid Woodhouse2014-02-01
| | | | | | | | | | This is a minimal implementation which accepts only constants rather than full expressions, but that should be perfectly sufficient for all known users for now. Patch from PaX Team <pageexec@freemail.hu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200614 91177308-0d34-0410-b5e6-96231b3b80d8
* Update a .fill test to use the updated semantics.David Majnemer2014-02-01
| | | | | | | Something funny happened, this should've been part of r200606. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200607 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Improve the .fill directive's compatibility with GASDavid Majnemer2014-02-01
| | | | | | | | | | Per the GAS documentation, .fill should permit pattern widths that aren't a power of two. While I was in the neighborhood, I added some sanity checking. This change was motivated by a use of this construct in the Linux Kernel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200606 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove another hasRawTextSupport.Rafael Espindola2014-01-31
| | | | | | | | | To remove this one simply move the end of file logic from the asm printer to the target mc streamer. This removes the last call to hasRawTextSupport from lib/Target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200590 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Add insert.d instruction.Matheus Almeida2014-01-31
| | | | | | | This instruction is only available on Mips64 cores that implement the MSA ASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200543 91177308-0d34-0410-b5e6-96231b3b80d8
* Move address override handling in X86MCCodeEmitter to a place where it works ↵Craig Topper2014-01-31
| | | | | | for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200516 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-30
| | | | | | | | | These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200495 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR18381 - print a minimal diagnostic rather than assert on unresolved ↵Timur Iskhodzhanov2014-01-30
| | | | | | .secidx target git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200490 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support .object_archSaleem Abdulrasool2014-01-30
| | | | | | | | | | The .object_arch directive indicates an alternative architecture to be specified in the object file. The directive does *not* effect the enabled feature bits for the object file generation. This is particularly useful when the code performs runtime detection and would like to indicate a lower architecture as the requirements than the actual instructions used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200451 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support .movspSaleem Abdulrasool2014-01-30
| | | | | | | | .movsp is an ARM unwinding directive that indicates to the unwinder that a register contains an offset from the current stack pointer. If the offset is unspecified, it defaults to zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200449 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: suuport .tlsdescseq directiveSaleem Abdulrasool2014-01-30
| | | | | | | | | | | This enhances the ARMAsmParser to handle .tlsdescseq directives. This is a slightly special relocation. We must be able to generate them, but not consume them in assembly. The relocation is meant to assist the linker in generating a TLS descriptor sequence. The ELF target streamer is enhanced to append additional fixups into the current segment and that is used to emit the new R_ARM_TLS_DESCSEQ relocations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200448 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: support TLS descriptor relocationsSaleem Abdulrasool2014-01-30
| | | | | | | | Add support for tlsdesc relocations which are part of the ABI, marked as experimental. These relocations permit the linker to perform TLS reference optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200447 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: support tlscall relocationsSaleem Abdulrasool2014-01-30
| | | | | | | | | | | | | | This adds support for TLS CALL relocations. TLS CALL relocations are used to indicate to the linker to generate appropriate entries to resolve TLS references via an appropriate function invocation (e.g. __tls_get_addr(PLT)). In order to accomodate the linker relaxation of the TLS access model for the references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete. This requires that the partial inplace value is also incomplete (i.e. 0). We simply avoid the offset value calculation at the time of the fixup adjustment in the ARM assembler backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200446 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Better management of macro argumentsDavid Majnemer2014-01-29
| | | | | | | | | | | | | The linux kernel makes uses of a GAS `feature' which substitutes nothing for macro arguments which aren't specified. Proper support for these kind of macro arguments necessitated a cleanup of differences between `GAS' and `Darwin' dialect macro processing. Differential Revision: http://llvm-reviews.chandlerc.com/D2634 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200409 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Add fill.d instruction.Matheus Almeida2014-01-29
| | | | | | | | | This instruction is only available on Mips64 cores that implement the MSA ASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200400 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Add copy_{u,s}.d.Matheus Almeida2014-01-29
| | | | | | | | | These instructions are only available on Mips64 cores that implement the MSA ASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200398 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable EHABI by defaultRenato Golin2014-01-29
| | | | | | | | | | | | | | | | | | | | | | After all hard work to implement the EHABI and with the test-suite passing, it's time to turn it on by default and allow users to disable it as a work-around while we fix the eventual bugs that show up. This commit also remove the -arm-enable-ehabi-descriptors, since we want the tables to be printed every time the EHABI is turned on for non-Darwin ARM targets. Although MCJIT EHABI is not working yet (needs linking with the right libraries), this commit also fixes some relocations on MCJIT regarding the EH tables/lib calls, and update some tests to avoid using EH tables when none are needed. The EH tests in the test-suite that were previously disabled on ARM now pass with these changes, so a follow-up commit on the test-suite will re-enable them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200388 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-07 23:53:35 +0000