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* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
* IndVarSimplify: check if loop invariant expansion can trapDavid Majnemer2013-06-04
| | | | | | | | | | | | | | | | IndVarSimplify is willing to move divide instructions outside of their loop bodies if they are invariant of the loop. However, it may not be safe to expand them if we do not know if they can trap. Instead, check to see if it is not safe to expand the instruction and skip the expansion. This fixes PR16041. Testcase by Rafael Ávila de Espíndola. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183239 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer2013-06-04
| | | | | | | | | | | The ARM backend did not expect LDRBi12 to hold a constant pool operand. Allow for LLVM to deal with the instruction similar to how it deals with LDRi12. This fixes PR16215. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183238 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Swizzle texture/export instructionsVincent Lejeune2013-06-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a test for r183108Vincent Lejeune2013-06-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183228 91177308-0d34-0410-b5e6-96231b3b80d8
* Second part of pr16069Rafael Espindola2013-06-04
| | | | | | | | | | | | | | | | | The problem this time seems to be a thinko. We were assuming that in the CFG A | \ | B | / C speculating the basic block B would cause only the phi value for the B->C edge to be speculated. That is not true, the phi's are semantically in the edges, so if the A->B->C path is taken, any code needed for A->C is not executed and we have to consider it too when deciding to speculate B. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183226 91177308-0d34-0410-b5e6-96231b3b80d8
* [llvm-symbolizer] Avoid calling slow getSymbolSize for Mach-O files. Assume ↵Alexey Samsonov2013-06-04
| | | | | | that symbols with zero size are in fact large enough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183213 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: Do not transform PHI to select if doing so would be unsafeDavid Majnemer2013-06-03
| | | | | | | | | | | | | | PR16069 is an interesting case where an incoming value to a PHI is a trap value while also being a 'ConstantExpr'. We do not consider this case when performing the 'HoistThenElseCodeToIf' optimization. Instead, make our modifications more conservative if we detect that we cannot transform the PHI to a select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183152 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable mcjit tests on ppc64 when building with cmake.Rafael Espindola2013-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183143 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Custom lower i64 sign_extendTom Stellard2013-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for global loadsTom Stellard2013-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183131 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: use capital letter for PV channelVincent Lejeune2013-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct handling invalid filename in llvm-symbolizerAlexey Samsonov2013-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183102 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju2013-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183094 91177308-0d34-0410-b5e6-96231b3b80d8
* [Object/COFF] Fix Windows .lib name handling.Rui Ueyama2013-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183091 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2013-06-03
| | | | | | | using two instructions (sethi and store). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183090 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju2013-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183088 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju2013-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183083 91177308-0d34-0410-b5e6-96231b3b80d8
* When determining the new index for an insertelement, we may not assume that anNick Lewycky2013-06-01
| | | | | | | | | | | index greater than the size of the vector is invalid. The shuffle may be shrinking the size of the vector. Fixes a crash! Also drop the maximum recursion depth of the safety check for this optimization to five. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183080 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ↵Venkatraman Govindaraju2013-06-01
| | | | | | as non-leaf functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183079 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable new legacy JIT test on ARM.Tim Northover2013-06-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183071 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-01
| | | | | | Very sorry, it was committed from the wrong branch by mistake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
* TMP: LEA64_32r fixingTim Northover2013-06-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183069 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-01
| | | | | | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. This fixes a typo in the opcode field of the original patch, which should make the legact JIT work again (& adds test for that problem). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju2013-06-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183067 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent loop-unroll from making assumptions about undefined behavior.Andrew Trick2013-05-31
| | | | | | | | | | | | | | Fixes rdar:14036816, PR16130. There is an opportunity to compute precise trip counts for 'or' expressions and multi-exit loops. rdar:14038809: Optimize trip count computation for multi-exit loops. To do this we need to record the fact that ExitLimit assumes NSW. When it does not we can safely assume that the loop trip count is the minimum ExitLimt across all subexpressions and loop exits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183060 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-31
| | | | | | seems to have caused PR16192 and other JIT related failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183059 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: PHIs with only outside users should prevent vectorizationArnold Schwaighofer2013-05-31
| | | | | | | | | | We check that instructions in the loop don't have outside users (except if they are reduction values). Unfortunately, we skipped this check for if-convertable PHIs. Fixes PR16184. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183035 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet2013-05-31
| | | | | | | | | | | | | | | Namely, check if the target allows to fold more that one register in the addressing mode and if yes, adjust the cost accordingly. Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2 needs a temporary register for the computation, whereas it was correctly estimated for reg1 + scale * reg2. <rdar://problem/13973908> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183021 91177308-0d34-0410-b5e6-96231b3b80d8
* Unit test for SCEV fix r182989, PR16130.Andrew Trick2013-05-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183017 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: permit upper-case BE/LE on setend instructionTim Northover2013-05-31
| | | | | | Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183012 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-31
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify multiplications by vectors whose elements are powers of 2.Rafael Espindola2013-05-31
| | | | | | Patch by Andrea Di Biagio. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183005 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix VEXT encoding corner caseTim Northover2013-05-31
| | | | | | | | | | The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford2013-05-31
| | | | | | | | | | | | | | | | | | | Unlike most -- hopefully "all other", but I'm still checking -- memory instructions we support, LOAD REVERSED and STORE REVERSED may access the memory location several times. This means that they are not suitable for volatile loads and stores. This patch is a prerequisite for better atomic load and store support. The same principle applies there: almost all memory instructions we support are inherently atomic ("block concurrent"), but LOAD REVERSED and STORE REVERSED are exceptions. Other instructions continue to allow volatile operands. I will add positive "allows volatile" tests at the same time as the "allows atomic load or store" tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183002 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2013-05-31
| | | | | | | | | | | | Now that 3.3 is branched, we are re-enabling virtual registers to help iron out bugs before the next release. Some of the post-RA passes do not play well with virtual registers, so we disable them for now. The needed functionality of the PrologEpilogInserter pass is copied to a new backend-specific NVPTXPrologEpilog pass. The test for this commit is not breaking the existing tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182998 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Handle mixed track-origins and keep-going settings (llvm part).Evgeniy Stepanov2013-05-31
| | | | | | | | | | | | | | | Before this change, each module defined a weak_odr global __msan_track_origins with a value of 1 if origin tracking is enabled, 0 if disabled. If there are modules with different values, any of them may win. If 0 wins, and there is at least one module with 1, the program will most likely crash. With this change, __msan_track_origins is only emitted if origin tracking is on. Then runtime library detects if there is at least one module with origin tracking, and enables runtime support for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182997 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-31
| | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182991 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Big-endian code generation for atomic instructions.Akira Hatanaka2013-05-31
| | | | | | | Patch by Jyun-Yan You. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182984 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply with r182909 with a fix to the calculation of the new indices forNick Lewycky2013-05-31
| | | | | | | insertelement instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182976 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r182937 and r182877.Rafael Espindola2013-05-30
| | | | | | | | | r182877 broke MCJIT tests on ARM and r182937 was working around another failure by r182877. This should make the ARM bots green. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182960 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use fast isel on this test.Rafael Espindola2013-05-30
| | | | | | | | This fixes the test on ARM. Looks like it was broken by r182877. Not sure if this is a bug on fast isel on ARM, but this should help fix the ARM bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182937 91177308-0d34-0410-b5e6-96231b3b80d8
* Force a triple so we don't get bitten by windows' different regalloc.Benjamin Kramer2013-05-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182935 91177308-0d34-0410-b5e6-96231b3b80d8
* Force fragile test to the atom scheduler model.Benjamin Kramer2013-05-30
| | | | | | | The pattern the test originally checked for doesn't occur on other -mcpu settings. On atom it's still there though slightly differently scheduled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182933 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: allow registers 8-15 in testTim Northover2013-05-30
| | | | | | | This test was failing on some hosts when an unexpected register was used for a variable. This just extends the regexp to allow the new x86-64 registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182929 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-30
| | | | | | | | | | | | Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
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