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* Changed the X86 assembler for intel syntax to work with directional labels.Kevin Enderby2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | The X86 assembler has a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following the Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197728 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86][fast-isel] Fix select lowering.Quentin Colombet2013-12-19
| | | | | | | | | | | The condition in selects is supposed to be i1. Make sure we are just reading the less significant bit of the 8 bits width value to match this constraint. <rdar://problem/15651765> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197712 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the .ltorg directive for ARM assemblyDavid Peixotto2013-12-19
| | | | | | | | | | | | | This directive will write out the assembler-maintained constant pool for the current section. These constant pools are created to support the ldr-pseudo instruction (e.g. ldr r0, =val). The directive can be used by the programmer to place the constant pool in a location that can be reached by a pc-relative offset in the ldr instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197711 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak ARM buildbots after r197653 by forcing the target triple on this test.Josh Magee2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197709 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the ldr-pseudo opcode for ARM assemblyDavid Peixotto2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ldr-pseudo opcode is a convenience for loading 32-bit constants. It is converted into a pc-relative load from a constant pool. For example, ldr r0, =0x10001 ldr r1, =bar will generate this output in the final assembly ldr r0, .Ltmp0 ldr r1, .Ltmp1 ... .Ltmp0: .long 0x10001 .Ltmp1: .long bar Sketch of the LDR pseudo implementation: Keep a map from Section => ConstantPool When parsing ldr r0, =val parse val as an MCExpr get ConstantPool for current Section Label = CreateTempSymbol() remember val in ConstantPool at next free slot add operand to ldr that is MCSymbolRef of Label On finishParse() callback Write out all non-empty constant pools for each Entry in ConstantPool Emit Entry.Label Emit Entry.Value Possible improvements to be added in a later patch: 1. Does not convert load of small constants to mov (e.g. ldr r0, =0x1 => mov r0, 0x1) 2. Does reuse constant pool entries for same constant The implementation was tested for ARM, Thumb1, and Thumb2 targets on linux and darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
* Move testcase to the appropriate X86 subdirectory.Adrian Prantl2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197701 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS control instructions.Zoran Jovanovic2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197696 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a disassembler to the PowerPC backendHal Finkel2013-12-19
| | | | | | | | | | | | | | | | | | | | | The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS LL and SC instructions.Zoran Jovanovic2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197692 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a triple so that this passes on OS X.Rafael Espindola2013-12-19
| | | | | | I am surprised I am the first one to notice this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197689 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS TLS relocations.Zoran Jovanovic2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197685 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an explicit insert point argument to SplitBlockAndInsertIfThen.Evgeniy Stepanov2013-12-19
| | | | | | | | | Currently SplitBlockAndInsertIfThen requires that branch condition is an Instruction itself, which is very inconvenient, because it is sometimes an Operator, or even a Constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197677 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the llvm-readobj COFF dumper to dump debug line tables from object filesTimur Iskhodzhanov2013-12-19
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D2425 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197674 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the COFF files with Z7 debug info from the repoTimur Iskhodzhanov2013-12-19
| | | | | | | Rationale: going to land D2425 shortly. I'll re-land these COFF files along with D2425 to simplify the SVN history git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197673 91177308-0d34-0410-b5e6-96231b3b80d8
* Add REQUIRES:asserts to 3 tests in llvm/test/CodeGen/R600 added in r192212.NAKAMURA Takumi2013-12-19
| | | | | | They are failing in assertions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197669 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Make private pointers be 32-bit.Matt Arsenault2013-12-19
| | | | | | | | Different sized address spaces should theoretically work most of the time now, and since 64-bit add is currently disabled, using more 32-bit pointers fixes some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197659 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support .inst directiveSaleem Abdulrasool2013-12-19
| | | | | | | | | This adds support for the .inst directive. This is an ARM specific directive to indicate an instruction encoded as a constant expression. The major difference between .word, .short, or .byte and .inst is that the latter will be disassembled as an instruction since it does not get flagged as data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197657 91177308-0d34-0410-b5e6-96231b3b80d8
* [stackprotector] Use analysis from the StackProtector pass for stack layout ↵Josh Magee2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | in PEI a nd LocalStackSlot passes. This changes the MachineFrameInfo API to use the new SSPLayoutKind information produced by the StackProtector pass (instead of a boolean flag) and updates a few pass dependencies (to preserve the SSP analysis). The stack layout follows the same approach used prior to this change - i.e., only LargeArray stack objects will be placed near the canary and everything else will be laid out normally. After this change, structures containing large arrays will also be placed near the canary - a case previously missed by the old implementation. Out of tree targets will need to update their usage of MachineFrameInfo::CreateStackObject to remove the MayNeedSP argument. The next patch will implement the rules for sspstrong and sspreq. The end goal is to support ssp-strong stack layout rules. WIP. Differential Revision: http://llvm-reviews.chandlerc.com/D2158 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197653 91177308-0d34-0410-b5e6-96231b3b80d8
* Begin adding docs and IR-level support for the inalloca attributeReid Kleckner2013-12-19
| | | | | | | | | | | | | | | | | | | The inalloca attribute is designed to support passing C++ objects by value in the Microsoft C++ ABI. It behaves the same as byval, except that it always implies that the argument is in memory and that the bytes are never copied. This attribute allows the caller to take the address of an outgoing argument's memory and execute arbitrary code to store into it. This patch adds basic IR support, docs, and verification. It does not attempt to implement any lowering or fix any possibly broken transforms. When this patch lands, a complete description of this feature should appear at http://llvm.org/docs/InAlloca.html . Differential Revision: http://llvm-reviews.chandlerc.com/D2173 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197645 91177308-0d34-0410-b5e6-96231b3b80d8
* add source in commentAdrian Prantl2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197642 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-cov: Added -f option for function summaries.Yuchen Wu2013-12-19
| | | | | | | | | | | Similar to the file summaries, the function summaries output line, branching and call statistics. The file summaries have been moved outside the initial loop so that all of the function summaries can be outputted before file summaries. Also updated test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197633 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a problem with mips16 stubs when calls are transformed duringReed Kotler2013-12-18
| | | | | | | | | | | tail call optimization. Some more work may be needed for indirect calls but this patch fixes the current regression in Prolangc++/trees. S2 optimization as part of the general cleanup and optimization of prolog and epilog was not saving S2 in this case and needed to. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197630 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Add -mcpu=z10 to SystemZ tests."Andrew Trick2013-12-18
| | | | | | | | | | This reverts commit r197466. The MachineCSE fix that required the -mcpu flag has been disabled until more work can be done to fix downstream issues. Adding -mcpu wasn't the right workaround anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197624 91177308-0d34-0410-b5e6-96231b3b80d8
* [aarch32] fix bug 18268: Incorrect condition of vselWeiming Zhao2013-12-18
| | | | | | | | | | Given vsel_cc, op1, op2, since vsel has no LE/LT, to generate vsel for such selection, it needs to inverse cc and swap op1 and op2. To inverse cc, both L/G and E bits should be flipped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197615 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info: Implement (rvalue) reference qualifiers for C++11 non-staticAdrian Prantl2013-12-18
| | | | | | | | member functions. Paired commit with CFE. rdar://problem/15356637 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197613 91177308-0d34-0410-b5e6-96231b3b80d8
* Correctly handle the degenerated triple "thumb".Rafael Espindola2013-12-18
| | | | | | | Fixes a crash in llc where some parts think the target is thumb and others think it is ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197607 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-cov: Print coverage summary to STDOUT.Yuchen Wu2013-12-18
| | | | | | | | | | | | File summaries will now be optionally outputted which will give line, branching and call coverage info. Unfortunately, clang's current instrumentation does not give enough information to deduce function calls, something that gcc is able to do. Thus, no calls are always outputted to be consistent with gcov output. Also updated tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197606 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-cov: Added -c option for branch counts.Yuchen Wu2013-12-18
| | | | | | | | | This will cause llvm-cov to output branch counts instead of branch probabilities. -b must be enabled. Also updated tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197594 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Update format of RUN lines for every MSA MC test.Matheus Almeida2013-12-18
| | | | | | | | | | | 1. The arch directive now appears before the cpu directive 2. Long run lines were split across multiple lines No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197588 91177308-0d34-0410-b5e6-96231b3b80d8
* One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.Rafael Espindola2013-12-18
| | | | | | | | Thanks for Iain Sandoe for testing this with the original gcc. Clang was already getting this right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197572 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Remove unneeded triple directive in MSA MC tests.Matheus Almeida2013-12-18
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197559 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: force soft-float ABI for tests depending on it.Tim Northover2013-12-18
| | | | | | This should fix the ARM bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197555 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: set default float ABI based on triple.Tim Northover2013-12-18
| | | | | | | | | | | | Clang sets the float-abi target option manually, but no longer annotates each function with its ABI. This can lead to confusing mistmatch between "clang -emit-llvm | llc" and normal clang invocations. Besides which, gnueabihf actually *is* hard-float. Defaulting to soft was just perverse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197554 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON]Implment loading vector constant form constant pool.Kevin Qin2013-12-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197551 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmParser: add support for .end directiveSaleem Abdulrasool2013-12-18
| | | | | | | | | | | | | | The .end directive indicates the end of the file. No further instructions are processed after a .end directive is encountered. One potential (glaringly obvious) optimisation that could be pursued here is to extend MCAsmParser with a DiscardRemainder method to avoid processing lexemes to the end of the file. It was unclear at this point if that would be worth adding, and could easily be added in a follow on change. Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197547 91177308-0d34-0410-b5e6-96231b3b80d8
* MC COFF: Emit the 'b' section flag for .bss sections in GNU assemblyReid Kleckner2013-12-17
| | | | | | | | | Without this, assembling clang's disassembly would produce an object file with the IMAGE_SCN_CNT_INITIALIZED_DATA section characteristic rather than the uninitialized one. link.exe would warn when merging comdats with different flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197529 91177308-0d34-0410-b5e6-96231b3b80d8
* Disabled subregister copy coalescing during MachineCSE.Andrew Trick2013-12-17
| | | | | | | | | This effectively backs out r197465 but leaves some of the general fixes in place. Not all targets are ready to handle this feature. To enable it, some infrastructure work is needed to better handle register class constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197514 91177308-0d34-0410-b5e6-96231b3b80d8
* Add warning capabilities in LLVM.Quentin Colombet2013-12-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reapplies r197438 and fixes the link-time circular dependency between IR and Support. The fix consists in moving the diagnostic support into IR. The patch adds a new LLVMContext::diagnose that can be used to communicate to the front-end, if any, that something of interest happened. The diagnostics are supported by a new abstraction, the DiagnosticInfo class. The base class contains the following information: - The kind of the report: What this is about. - The severity of the report: How bad this is. This patch also adds 2 classes: - DiagnosticInfoInlineAsm: For inline asm reporting. Basically, this diagnostic will be used to switch to the new diagnostic API for LLVMContext::emitError. - DiagnosticStackSize: For stack size reporting. Comes as a replacement of the hard coded warning in PEI. This patch also features dynamic diagnostic identifiers. In other words plugins can use this infrastructure for their own diagnostics (for more details, see getNextAvailablePluginDiagnosticKind). This patch introduces a new DiagnosticHandlerTy and a new DiagnosticContext in the LLVMContext that should be set by the front-end to be able to map these diagnostics in its own system. http://llvm-reviews.chandlerc.com/D2376 <rdar://problem/15515174> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197508 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix off by one issue when applying a fixup.Matheus Almeida2013-12-17
| | | | | | | | | The branch offset for a R_MIPS_PC16 relocation is indeed a 16-bit signed immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197506 91177308-0d34-0410-b5e6-96231b3b80d8
* Setting the CPU in the new vaargs testDuncan P. N. Exon Smith2013-12-17
| | | | | | | | Trying to fix buildbots after r197503 (test passes locally). <rdar://problem/15627766> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197505 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "Mark vastart_save_xmm_regs as changing EFLAGS""Duncan P. N. Exon Smith2013-12-17
| | | | | | | | | | | | | | | | | | | This reverts commit r197481, recommiting r197469 with an extra fix. The vastart_save_xmm_regs pseudo-instruction expands to a test and a branch, so it modifies EFLAGS. Mark it so, or else the scheduler might place it in the middle of another test+branch. This fixes a bug exposed by r192750, which changed the initial scheduler to source-order as part of enabling the MI Scheduler for X86. This re-commit changes the VASTART_SAVE_XMM_REGS custom inserter not to try to save %flags, and adds a test that catches the bad behavior of r197469. <rdar://problem/15627766> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197503 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some simple COFF files with Z7 debug infoTimur Iskhodzhanov2013-12-17
| | | | | | These will later be used as tests for the dumper part of http://llvm-reviews.chandlerc.com/D2232 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197499 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18045:Stepan Dyatkovskiy2013-12-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://llvm.org/bugs/show_bug.cgi?id=18045 Short issue description: For X86 machines with sse < sse4.1 we got failures for some particular load/store vector sequences: $ clang-trunk -m32 -O2 test-case.c fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850, 0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82] [ID=58] 0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43] 0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23] 0x41dcb10: i32 = undef [ID=2] The reason is that EltsFromConsecutiveLoads could emit such load instruction both before and after legalize stage. Though this instruction is not legal for machines with SSSE3 and lower. The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we check whether nodes it emits are legal. P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8), perhaps I'll slow with response, so you better reject this commit. Thanks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197492 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey ↵Elena Demikhovsky2013-12-17
| | | | | | | | | Bader). Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197482 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Mark vastart_save_xmm_regs as changing EFLAGS"Duncan P. N. Exon Smith2013-12-17
| | | | | | | | | This reverts commit r197469. The sanitizer and dragonegg buildbots are failing, I think because of this change. Reverting until I figure out why. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197481 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark vastart_save_xmm_regs as changing EFLAGSDuncan P. N. Exon Smith2013-12-17
| | | | | | | | | | | | | The vastart_save_xmm_regs pseudo-instruction expands to a test and a branch, so it modifies EFLAGS. Mark it so, or else the scheduler might place it in the middle of another test+branch. This fixes a bug exposed by r192750, which turned on the MI Scheduler for X86. <rdar://problem/15627766> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197469 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -mcpu=z10 to SystemZ tests.Andrew Trick2013-12-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197466 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow MachineCSE to coalesce trivial subregister copies the same way that it ↵Andrew Trick2013-12-17
| | | | | | | | | | | | | | | | | | | | coalesces normal copies. Without this, MachineCSE is powerless to handle redundant operations with truncated source operands. This required fixing the 2-addr pass to handle tied subregisters. It isn't clear what combinations of subregisters can legally be tied, but the simple case of truncated source operands is now safely handled: %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1 %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2 %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def> Test case: cse-add-with-overflow.ll. This exposed an existing bug in PPCInstrInfo::commuteInstruction. Thanks to Rafael for the test case: PowerPC/crash.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197465 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r197438 and r197447 until we figure out how to avoid circular ↵Quentin Colombet2013-12-17
| | | | | | dependency at link time git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197451 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Don't if-convert constant expressions that can trapArnold Schwaighofer2013-12-17
| | | | | | | | | | A phi node operand or an instruction operand could be a constant expression that can trap (division). Check that we don't vectorize such cases. PR16729 radar://15653590 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197449 91177308-0d34-0410-b5e6-96231b3b80d8
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