summaryrefslogtreecommitdiff
path: root/test
Commit message (Expand)AuthorAge
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-13
* Clean up LDV, no functionality change.Manman Ren2013-02-13
* PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIADavid Peixotto2013-02-13
* X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer2013-02-13
* Make jumptables work for -staticReed Kotler2013-02-13
* Prevent insertion of "vzeroupper" before call that preserves YMM registers, s...Elena Demikhovsky2013-02-13
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-13
* Finish obviously broken thought.Eric Christopher2013-02-13
* [tsan] disable load widening in ThreadSanitizer modeKostya Serebryany2013-02-13
* Debug Info: LiveDebugVarible can remove DBG_VALUEs, make sure we emit them back.Manman Ren2013-02-13
* Remove target-specific info from the testcase for DWARF/pubnames.Krzysztof Parzyszek2013-02-12
* [ms-inline asm] Add support for lexing binary integers with a [bB] suffix.Chad Rosier2013-02-12
* Allow optionally generating pubnames section in DWARF info. IntroduceKrzysztof Parzyszek2013-02-12
* added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo2013-02-12
* Fix the lit test added in r174972Paul Redmond2013-02-12
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-12
* PR14562 - Truncation of left shift became undefPaul Redmond2013-02-12
* [NVPTX] Disable vector registersJustin Holewinski2013-02-12
* [asan] fix tests for the new ABIKostya Serebryany2013-02-12
* Test for string attributes and for attribute group output.Bill Wendling2013-02-12
* ARM cost model: Add vector reverse shuffle costsArnold Schwaighofer2013-02-12
* ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer2013-02-12
* [ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.Chad Rosier2013-02-12
* Optimization: bitcast (<1 x ...> insertelement ..., X, ...) to ... ==> bitcas...Michael Ilseman2013-02-11
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-11
* Remove trailing whitespaceMichael Ilseman2013-02-11
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-11
* [NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture ...Justin Holewinski2013-02-11
* AArch64: generate dwarfdump test rather than include .o in subversionTim Northover2013-02-11
* AArch64: Add basic relocation processing for llvm-dwarfdump.Tim Northover2013-02-11
* AArch64: Undo change to how test was runTim Northover2013-02-11
* Make use of DiagnosticType to provide better AArch64 diagnostics.Tim Northover2013-02-11
* FileCheck-ize the tests.Bill Wendling2013-02-11
* [tsan/msan] adding thread_safety and uninitialized_checks attributesKostya Serebryany2013-02-11
* LSR IVChain improvement.Andrew Trick2013-02-09
* Dwarf: do not use line_table_start in at_stmt_list since we do not always emit Manman Ren2013-02-09
* Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are theReed Kotler2013-02-08
* DAGCombiner: Constant folding around pre-increment loads/storesHal Finkel2013-02-08
* Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.Bob Wilson2013-02-08
* Refine fix to bug 15041.Bill Schmidt2013-02-08
* [SimplifyLibCalls] Library call simplification doen't work if the call site Chad Rosier2013-02-08
* ARM cost model: Address computation in vector mem ops not freeArnold Schwaighofer2013-02-08
* Update tests for DWARF parser: store sources next to pre-built object files a...Alexey Samsonov2013-02-08
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-08
* Revert "Have InstCombine call SipmlifyCall when handling calls. Test case inc...Andrew Trick2013-02-08
* Have InstCombine call SipmlifyCall when handling calls. Test case included.Michael Ilseman2013-02-07
* [mips] Add definition of JALR instruction which has two register operands. Ch...Akira Hatanaka2013-02-07
* Identify and simplify idempotent intrinsics. Test case included.Michael Ilseman2013-02-07
* [Object][ELF] Fix crash on no dynamic section.Michael J. Spencer2013-02-07
* ARM cost model: Add costs for vector selectsArnold Schwaighofer2013-02-07