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* Emit arange padding with a single directive.Benjamin Kramer2014-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198700 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64David Peixotto2014-01-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the pre-UAL aliases of fconsts and fconstd for vmov.f32 and vmov.f64. They use an InstAlias rather than a MnemonicAlias to properly support the predicate operand. We need to support encoded 8-bit constants in order to implement the pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this commit also fixes parsing of encoded floating point constants used in vmov.f32/vmov.f64 instructions. Now we can support assembly code like this: fconsts s0, #0x70 which is equivalent to vmov.f32 s0, #1.0. Most of the code was already in place to support this feature. Previously the code was trying to accept encoded 8-bit float constants for the vmov.f32/vmov.f64 instructions. It looks like the support for parsing encoded floats was lost in a refactoring in commit r148556 and we did not have any tests in place to catch it. The change in this commit is to keep the parsed value as a 32-bit float instead of a 64-bit double because that is what the isFPImm() function expects to find. There is no loss of precision by using a 32-bit float here because we are still limited to an 8-bit encoded value in the end. Additionally, we explicitly reject encoded 8-bit floats for vmovf.32/64. This is the same as the current behavior, but we now do it explicitly rather than accidently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198697 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. ↵Hao Liu2014-01-07
| | | | | | There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198684 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Add support to copy D tuples such as DPair/DTriple/DQuad and Q ↵Hao Liu2014-01-07
| | | | | | tuples such as QPair/QTriple/QQuad. There is no test case for D tuple as the original test cases are too large. As the copy of the D tuple is similar to the Q tuple, the correctness can be guaranteed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198682 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc., Venkatraman Govindaraju2014-01-07
| | | | | | | Also, correct the offsets for FixupsKindInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198681 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18396: Assertion: MO->isDead "Cannot fold physreg def".Andrew Trick2014-01-07
| | | | | | InlineSpiller::foldMemoryOperand needs to handle undef call operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198679 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r198654 "indvars: sink truncates outside the loop."Andrew Trick2014-01-07
| | | | | | | | | | | This doesn't seem to have actually broken anything. It was paranoia on my part. Trying again now that bots are more stable. This is a follow up of the r198338 commit that added truncates for lcssa phi nodes. Sinking the truncates below the phis cleans up the loop and simplifies subsequent analysis within the indvars pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198678 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fixed incorrect immediate used in BIC instruction.Kevin Qin2014-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198675 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: allow more depth in contextual diagnosticsSaleem Abdulrasool2014-01-07
| | | | | | | Switch the context to be SmallVectors. This allows for saving additional context when providing previous emission sites. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198665 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: refactor unwind contextSaleem Abdulrasool2014-01-07
| | | | | | | | Move the unwinding context for the ARM IAS into a helper class. This is purely a structural refactoring. A follow up change allows for recording additional depth to improve diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198664 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: improve .eabi_attribute handlingSaleem Abdulrasool2014-01-07
| | | | | | | | Parse tag names as well as expressions. The former is part of the specification, the latter is for improved compatibility with the GNU assembler. Fix attribute value handling to be comformant to the specification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198662 91177308-0d34-0410-b5e6-96231b3b80d8
* MCParser: introduce Note and use it for ARM AsmParserSaleem Abdulrasool2014-01-07
| | | | | | | | Introduce a new virtual method Note into the AsmParser. This completements the existing Warning and Error methods. Use the new method to clean up the output of the unwind routines in the ARM AsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198661 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "indvars: sink truncates outside the loop."Andrew Trick2014-01-07
| | | | | | | | This reverts commit r198654. One of the bots reported a SciMark failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198659 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing memory operands in sparc AsmParser.Venkatraman Govindaraju2014-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198658 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars: sink truncates outside the loop.Andrew Trick2014-01-07
| | | | | | | | This is a follow up of the r198338 commit that added truncates for lcssa phi nodes. Sinking the truncates below the phis cleans up the loop and simplifies subsequent analysis within the indvars pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198654 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] TargetStreamer Support for .abicalls and .set pic0.Jack Carter2014-01-06
| | | | | | | | | | | This patch adds .abicalls and .set pic0 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that both the integrated and standalone assemblers will use for the output for these directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198646 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r198478 "Fix PR18361: Invalidate LoopDispositions after LoopSimplify ↵Andrew Trick2014-01-06
| | | | | | | | | | hoists things." Now with a fix for PR18384: ValueHandleBase::ValueIsDeleted. We need to invalidate SCEV's loop info when we delete a block, even if no values are hoisted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198631 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.Tim Northover2014-01-06
| | | | | | | | | | | | | | | | | | The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198617 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore Target: correct callee save register spilling when callsUnwindInit is ↵Robert Lytton2014-01-06
| | | | | | true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198616 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Lower EH_RETURNRobert Lytton2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198615 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Lower FRAME_TO_ARGS_OFFSETRobert Lytton2014-01-06
| | | | | | | | | This requires a knowledge of the stack size which is not known until the frame is complete, hence the need for the XCoreFTAOElim pass which lowers the XCoreISD::FRAME_TO_ARGS_OFFSET instrution into its final form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198614 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Lower RETURNADDRRobert Lytton2014-01-06
| | | | | | Only handles a depth of zero (the same as FRAMEADDR) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198613 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Optimise entsp / retsp selectionRobert Lytton2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198612 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: fix handling of unsized global arrays in large code modelRobert Lytton2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198609 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: keep special non-AEABIness of "-darwin-eabi" triples for nowTim Northover2014-01-06
| | | | | | | | | | Longer term, we want to move users to "*-*-*-macho" for embedded work, but for now people are relying on the last thing we told them, which is unfortunately "*-*-darwin-eabi". rdar://problem/15703934 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198602 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without)Elena Demikhovsky2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198593 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add initial implementation of disassembler for sparcVenkatraman Govindaraju2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198591 91177308-0d34-0410-b5e6-96231b3b80d8
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-06
| | | | | | | | | | | | | | | | | | | The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198586 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add basic support for .code16Craig Topper2014-01-06
| | | | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198584 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fix invalid constant used in vselect condition.Kevin Qin2014-01-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is a wrong assumption that the vector element type and the type of each ConstantSDNode in the build_vector were the same. However, when promoting the integer operand of a legally typed build_vector, the operand type and the vector element type do not need to be the same (See method 'DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR' in LegalizeIntegerTypes.cpp). in AArch64 backend, the following dag sequence: C0: i1 = Constant<0> C1: i1 = Constant<-1> V: v8i1 = BUILD_VECTOR C1, C1, C0, C0, C0, C0, C0, C0 is type-legalized into: NewC0: i32 = Constant<0> NewC1: i32 = Constant<1> V: v8i8 = BUILD_VECTOR NewC1, NewC1, NewC0, NewC0, NewC0, NewC0, NewC0, NewC0 Forcing a getZeroExtend to VTBits to ensure that the new constant is correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198582 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a failing test to get the buildbots back to green.Bill Wendling2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198578 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to fix s390x build bot.Bill Wendling2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198577 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ModR/M byte output for 16-bit addressing modes (PR18220)Craig Topper2014-01-05
| | | | | | | | | | | Add some tests to validate correct register selection, including a fix to an existing test which was requiring the *wrong* output. Patch from David Woodhouse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198566 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: changed property name from "neverHasSideEffects=1" to ↵Elena Demikhovsky2014-01-05
| | | | | | | | | "hasSideEffects=0", added this property to VMOVSS/VMOVSD; Optimized a truncate pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198562 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] Add support for DT_MIPS_RLD_MAP and DT_MIPS_PLTGOT dynamicSimon Atanasyan2014-01-05
| | | | | | section tags to the llvm-readobj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198561 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] Rename the test case input file. No functional changes.Simon Atanasyan2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198560 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added more intrinsics for convert and min/max.Elena Demikhovsky2014-01-05
| | | | | | | Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198557 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to fix buildbots by XFAILing some architectures.Bill Wendling2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198537 91177308-0d34-0410-b5e6-96231b3b80d8
* Add lit.local.cfg for MC/SparcVenkatraman Govindaraju2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198536 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add initial implementation of MC Code emitter for sparc.Venkatraman Govindaraju2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198533 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit an error message if the value passed to __builtin_returnaddress isn't a ↵Bill Wendling2014-01-05
| | | | | | | | | | constant __builtin_returnaddress requires that the value passed into is be a constant. However, at -O0 even a constant expression may not be converted to a constant. Emit an error message intead of crashing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198531 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the ↵Craig Topper2014-01-05
| | | | | | corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198530 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Fix PR18361: Invalidate LoopDispositions after LoopSimplify hoists ↵Alp Toker2014-01-04
| | | | | | | | | | | | | | | | | things." This commit was the source of crasher PR18384: While deleting: label %for.cond127 An asserting value handle still pointed to this value! UNREACHABLE executed at llvm/lib/IR/Value.cpp:671! Reverting to get the builders green, feel free to re-land after fixing up. (Renato has a handy isolated repro if you need it.) This reverts commit r198478. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198503 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64. Venkatraman Govindaraju2014-01-04
| | | | | | | Fixes PR18356. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198480 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR18361: Invalidate LoopDispositions after LoopSimplify hoists things.Andrew Trick2014-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getSCEV for an ashr instruction creates an intermediate zext expression when it truncates its operand. The operand is initially inside the loop, so the narrow zext expression has a non-loop-invariant loop disposition. LoopSimplify then runs on an outer loop, hoists the ashr operand, and properly invalidate the SCEVs that are mapped to value. The SCEV expression for the ashr is now an AddRec with the hoisted value as the now loop-invariant start value. The LoopDisposition of this wide value was properly invalidated during LoopSimplify. However, if we later get the ashr SCEV again, we again try to create the intermediate zext expression. We get the same SCEV that we did earlier, and it is still cached because it was never mapped to a Value. When we try to create a new AddRec we abort because we're using the old non-loop-invariant LoopDisposition. I don't have a solution for this other than to clear LoopDisposition when LoopSimplify hoists things. I think the long-term strategy should be to perform LoopSimplify on all loops before computing SCEV and before running any loop opts on individual loops. It's possible we may want to rerun LoopSimplify on individual loops, but it should rarely do anything, so rarely require invalidating SCEV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198478 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64][NEON] Added SXTL and SXTL2 instruction aliasesAna Pazos2014-01-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198437 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "Debug Info: Type Units: Simplify type hashing using ↵David Blaikie2014-01-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | IR-provided unique names."" This reverts commit r198398, thus reapplying r198397. I had accidentally introduced an endianness issue when applying the hash to the type unit. Using support::ulittle64_t in the reinterpret_cast in addDwarfTypeUnitType fixes this issue. Original commit message: Debug Info: Type Units: Simplify type hashing using IR-provided unique names. What's good for LTO metadata size problems ought to be good for non-LTO debug info size too, so let's rely on the same uniqueness in both cases. If it's insufficient for non-LTO for whatever reason (since we now won't be uniquing CU-local types or any C types - but these are likely to not be the most significant contributors to type bloat) we should consider a frontend solution that'll help both LTO and non-LTO alike, rather than using DWARF-level DIE-hashing that only helps non-LTO debug info size. It's also much simpler this way and benefits C++ even more since we can deduplicate lexically separate definitions of the same C++ type since they have the same mangled name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198436 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix loop rerolling pass failure with non-consant loop lower boundDavid Peixotto2014-01-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The loop rerolling pass was failing with an assertion failure from a failed cast on loops like this: void foo(int *A, int *B, int m, int n) { for (int i = m; i < n; i+=4) { A[i+0] = B[i+0] * 4; A[i+1] = B[i+1] * 4; A[i+2] = B[i+2] * 4; A[i+3] = B[i+3] * 4; } } The code was casting the SCEV-expanded code for the new induction variable to a phi-node. When the loop had a non-constant lower bound, the SCEV expander would end the code expansion with an add insted of a phi node and the cast would fail. It looks like the cast to a phi node was only needed to get the induction variable value coming from the backedge to compute the end of loop condition. This patch changes the loop reroller to compare the induction variable to the number of times the backedge is taken instead of the iteration count of the loop. In other words, we stop the loop when the current value of the induction variable == IterationCount-1. Previously, the comparison was comparing the induction variable value from the next iteration == IterationCount. This problem only seems to occur on 32-bit targets. For some reason, the loop is not rerolled on 64-bit targets. PR18290 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198425 91177308-0d34-0410-b5e6-96231b3b80d8
* BasicAA: Use reachabilty instead of dominance for checking value equality in phiArnold Schwaighofer2014-01-03
| | | | | | | | | | | | | | | | | | | | | cycles This allows the value equality check to work even if we don't have a dominator tree. Also add some more comments. I was worried about compile time impacts and did not implement reachability but used the dominance check in the initial patch. The trade-off was that the dominator tree was required. The llvm utility function isPotentiallyReachable cuts off the recursive search after 32 visits. Testing did not show any compile time regressions showing my worries unjustfied. No compile time or performance regressions at O3 -flto -mavx on test-suite + externals. Addresses review comments from r198290. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198400 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Debug Info: Type Units: Simplify type hashing using IR-provided ↵David Blaikie2014-01-03
| | | | | | | | | | | unique names." Reverting due to bot failure I won't have time to investigate until tomorrow. This reverts commit r198397. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198398 91177308-0d34-0410-b5e6-96231b3b80d8
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