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* Revert r198851, "Prototype of skeleton type units for fission"NAKAMURA Takumi2014-01-09
| | | | | | It caused undefined behavior. DwarfTypeUnit::Ty might not be initialized properly, I guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198865 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed old typo in ScalarEvolution, that caused wrong SCEVs zext operation.Stepan Dyatkovskiy2014-01-09
| | | | | | | | | | | Detailed description is here: http://llvm.org/bugs/show_bug.cgi?id=18000#c16 For participation in bugfix process special thanks to David Wiberg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198863 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Fix RNSBG bug introduced by r197802Richard Sandiford2014-01-09
| | | | | | | | | The zext handling added in r197802 wasn't right for RNSBG. This patch restricts it to ROSBG, RXSBG and RISBG. (The tests for RISBG were added in r197802 since RISBG was the motivating example.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198862 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle masked rotate amountsRichard Sandiford2014-01-09
| | | | | | | | | | | | | | | At the moment we expect rotates to have the form: (or (shl X, Y), (shr X, Z)) where Y == bitsize(X) - Z or Z == bitsize(X) - Y. This form means that the (or ...) is undefined for Y == 0 or Z == 0. This undefinedness can be avoided by using Y == (C * bitsize(X) - Z) & (bitsize(X) - 1) or Z == (C * bitsize(X) - Y) & (bitsize(X) - 1) for any integer C (including 0, the most natural choice). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198861 91177308-0d34-0410-b5e6-96231b3b80d8
* Match the InstCombine form of rotates by X+CRichard Sandiford2014-01-09
| | | | | | | | | | | | | | | | | | InstCombine converts (sub 32, (add X, C)) into (sub 32-C, X), so a rotate left of a 32-bit Y by X+C could appear as either: (or (shl Y, (add X, C)), (shr Y, (sub 32, (add X, C)))) without InstCombine or: (or (shl Y, (add X, C)), (shr Y, (sub 32-C, X))) with it. We already matched the first form. This patch handles the second too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198860 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an "-object-cache-dir=<string>" option to LLI. This option specifies theLang Hames2014-01-09
| | | | | | | | | | | | | root path to which object files managed by the LLIObjectCache instance should be written. This option defaults to "", in which case objects are cached in the same directory as the bitcode they are derived from. The load-object-a.ll test has been rewritten to use this option to support testing in environments where the test directory is not writable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198852 91177308-0d34-0410-b5e6-96231b3b80d8
* Prototype of skeleton type units for fissionDavid Blaikie2014-01-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198851 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-readobj: address review comments for ARM EHABI printingSaleem Abdulrasool2014-01-09
| | | | | | | | Rename bytecode to opcodes to make it more clear. Change an impossible case to llvm_unreachable instead. Avoid allocation of a buffer by modifying the PrintOpcodes iteration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198848 91177308-0d34-0410-b5e6-96231b3b80d8
* DwarfDebug: Refactor out common skeleton construction code to be reused for ↵David Blaikie2014-01-09
| | | | | | type unit skeletons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198846 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm.experimental.stackmap: fix encoding of large constants.Andrew Trick2014-01-09
| | | | | | | | | | In the stackmap format we advertise the constant field as signed. However, we were determining whether to promote to a 64-bit constant pool based on an unsigned comparison. This fix allows -1 to be encoded as a small constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198816 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-dwarfdump: reorder dwo sections to immediately proceed their non-dwo ↵David Blaikie2014-01-08
| | | | | | | | | equivalents This makes it easier to write a test that's mostly shared between fission and non-fission (using FileCheck's multiple prefix support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198806 91177308-0d34-0410-b5e6-96231b3b80d8
* Conservatively handle multiple MMOs in MIsNeedChainEdgeHal Finkel2014-01-08
| | | | | | | | | | | | | | | | | | | | | | MIsNeedChainEdge, which is used by -enable-aa-sched-mi (AA in misched), had an llvm_unreachable when -enable-aa-sched-mi is enabled and we reach an instruction with multiple MMOs. Instead, return a conservative answer. This allows testing -enable-aa-sched-mi on x86. Also, this moves the check above the isUnsafeMemoryObject checks. isUnsafeMemoryObject is currently correct only for instructions with one MMO (as noted in the comment in isUnsafeMemoryObject): // We purposefully do no check for hasOneMemOperand() here // in hope to trigger an assert downstream in order to // finish implementation. The problem with this is that, had the candidate edge passed the "!MIa->mayStore() && !MIb->mayStore()" check, the hoped-for assert would never happen (which could, in theory, lead to incorrect behavior if one of these secondary MMOs was volatile, for example). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198795 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64][NEON] Added UXTL and UXTL2 instruction aliasesAna Pazos2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198791 91177308-0d34-0410-b5e6-96231b3b80d8
* Force emit a relocation for @gnu_indirect_function symbols so that the indirectRoman Divacky2014-01-08
| | | | | | | resolution works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198780 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the DAGCombiner how to fold 'vselect' dag nodes accordingAndrea Di Biagio2014-01-08
| | | | | | | | | | to the following two rules: 1) fold (vselect (build_vector AllOnes), A, B) -> A 2) fold (vselect (build_vector AllZeros), A, B) -> B git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198777 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing test case for r198737.Lang Hames2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198772 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Support R_386_PC8, R_386_PC16 and R_X86_64_PC8David Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198763 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Do not relax PUSHi16 to PUSHi32 (PR18414)David Woodhouse2014-01-08
| | | | | | | | They do *different* things to %esp, so they are not equivalent. Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198761 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Make AsmParser validate registers for memory operands a bit betterDavid Woodhouse2014-01-08
| | | | | | | | | | | | We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198760 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-08
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Use 16-bit addressing where possible in 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | | | Where "where possible" means that it's an immediate value and it's below 0x10000. In fact GAS will either truncate or error with larger values, and will insist on using the addr32 prefix to get 32-bit addressing. So perhaps we should do that, in a later patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198758 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix JCXZ,JECXZ_32 for 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that appropriately conditional. And JECXZ needs the prefix instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198757 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Disambiguate RET[QL] and fix aliases for 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | | | | I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198756 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliasesDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliasesDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198754 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit modeDavid Woodhouse2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198753 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-08
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198752 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq.Elena Demikhovsky2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198745 91177308-0d34-0410-b5e6-96231b3b80d8
* [patch] Adjust behavior of FDE cross-section relocs for targets that don't ↵Iain Sandoe2014-01-08
| | | | | | | | | | | | | | support abs-differences. Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs. This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff". At present, this is only enabled for modern x86 OSX ports. test changes by David Fang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198744 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fix generating incorrect value type of NEON_VDUPLANEKevin Qin2014-01-08
| | | | | | | when lower build_vector if result value type mismatch with operand value type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198743 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9] Rename operands in some sparc64 instructions so that TableGen can ↵Venkatraman Govindaraju2014-01-08
| | | | | | encode them correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198740 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing branch instructions and conditional moves.Venkatraman Govindaraju2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198738 91177308-0d34-0410-b5e6-96231b3b80d8
* tests: disable ARM unwinding tests if ARM is unavailableSaleem Abdulrasool2014-01-08
| | | | | | | | | | Appease the buildbots for targets which do not build the ARM support by moving the ARM specific test into a subdirectory and use the lit configuration to disable them appropriately. Thanks to chapuni and thakis for explaining how to do this! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198736 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: properly handle expression operandsSaleem Abdulrasool2014-01-08
| | | | | | | Operands which involved label arithemetic would previously fail to parse. This corrects that by adding the additional case for the shift operand validation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198735 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-readobj: add support for ARM EHABI unwind infoSaleem Abdulrasool2014-01-08
| | | | | | | | | | | | | | | This adds some preliminary support for decoding ARM EHABI unwinding information. The major functionality that remains from complete support is bytecode translation. Each Unwind Index Table is printed out as a separate entity along with its section index, name, offset, and entries. Each entry lists the function address, and if possible, the name, of the function to which it corresponds. The encoding model, personality routine or index, and byte code is also listed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198734 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug about generating undef operand when optimising shuffle vector and ↵Hao Liu2014-01-08
| | | | | | insert element in instruction combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198730 91177308-0d34-0410-b5e6-96231b3b80d8
* In the ELFWriter when writing aliased (.set) symbols dont blindlyRoman Divacky2014-01-07
| | | | | | | | | | | | | take type from the new symbol but merge them so that the type is never "downgraded". This is probably quite rare, except for IFUNC symbols which we used to misassemble, losing the IFUNC type. Fixes #18372. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198706 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assert with private type info variables.Rafael Espindola2014-01-07
| | | | | | | With the gnu objc runtime private strings are used. Since we only need to produce a unique label, the fix is to just drop the asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198701 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit arange padding with a single directive.Benjamin Kramer2014-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198700 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64David Peixotto2014-01-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the pre-UAL aliases of fconsts and fconstd for vmov.f32 and vmov.f64. They use an InstAlias rather than a MnemonicAlias to properly support the predicate operand. We need to support encoded 8-bit constants in order to implement the pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this commit also fixes parsing of encoded floating point constants used in vmov.f32/vmov.f64 instructions. Now we can support assembly code like this: fconsts s0, #0x70 which is equivalent to vmov.f32 s0, #1.0. Most of the code was already in place to support this feature. Previously the code was trying to accept encoded 8-bit float constants for the vmov.f32/vmov.f64 instructions. It looks like the support for parsing encoded floats was lost in a refactoring in commit r148556 and we did not have any tests in place to catch it. The change in this commit is to keep the parsed value as a 32-bit float instead of a 64-bit double because that is what the isFPImm() function expects to find. There is no loss of precision by using a 32-bit float here because we are still limited to an 8-bit encoded value in the end. Additionally, we explicitly reject encoded 8-bit floats for vmovf.32/64. This is the same as the current behavior, but we now do it explicitly rather than accidently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198697 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. ↵Hao Liu2014-01-07
| | | | | | There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198684 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Add support to copy D tuples such as DPair/DTriple/DQuad and Q ↵Hao Liu2014-01-07
| | | | | | tuples such as QPair/QTriple/QQuad. There is no test case for D tuple as the original test cases are too large. As the copy of the D tuple is similar to the Q tuple, the correctness can be guaranteed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198682 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc., Venkatraman Govindaraju2014-01-07
| | | | | | | Also, correct the offsets for FixupsKindInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198681 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18396: Assertion: MO->isDead "Cannot fold physreg def".Andrew Trick2014-01-07
| | | | | | InlineSpiller::foldMemoryOperand needs to handle undef call operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198679 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r198654 "indvars: sink truncates outside the loop."Andrew Trick2014-01-07
| | | | | | | | | | | This doesn't seem to have actually broken anything. It was paranoia on my part. Trying again now that bots are more stable. This is a follow up of the r198338 commit that added truncates for lcssa phi nodes. Sinking the truncates below the phis cleans up the loop and simplifies subsequent analysis within the indvars pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198678 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fixed incorrect immediate used in BIC instruction.Kevin Qin2014-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198675 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: allow more depth in contextual diagnosticsSaleem Abdulrasool2014-01-07
| | | | | | | Switch the context to be SmallVectors. This allows for saving additional context when providing previous emission sites. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198665 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: refactor unwind contextSaleem Abdulrasool2014-01-07
| | | | | | | | Move the unwinding context for the ARM IAS into a helper class. This is purely a structural refactoring. A follow up change allows for recording additional depth to improve diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198664 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: improve .eabi_attribute handlingSaleem Abdulrasool2014-01-07
| | | | | | | | Parse tag names as well as expressions. The former is part of the specification, the latter is for improved compatibility with the GNU assembler. Fix attribute value handling to be comformant to the specification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198662 91177308-0d34-0410-b5e6-96231b3b80d8
* MCParser: introduce Note and use it for ARM AsmParserSaleem Abdulrasool2014-01-07
| | | | | | | | Introduce a new virtual method Note into the AsmParser. This completements the existing Warning and Error methods. Use the new method to clean up the output of the unwind routines in the ARM AsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198661 91177308-0d34-0410-b5e6-96231b3b80d8
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