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* [X86] Improve the selection of SSE3/AVX addsub instructions. Andrea Di Biagio2014-06-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches the backend how to canonicalize a shuffle vectors according to the rule: - (shuffle (FADD A, B), (FSUB A, B), Mask) -> (shuffle (FSUB A, -B), (FADD A, -B), Mask) Where 'Mask' is: <0,5,2,7> ;; for v4f32 and v4f64 shuffles. <0,3> ;; for v2f64 shuffles. <0,9,2,11,4,13,6,15> ;; for v8f32 shuffles. In general, ISel only knows how to pattern-match a canonical 'fadd + fsub + blendi' dag node sequence into an ADDSUB instruction. This new rule allows to convert a non-canonical dag sequence into a canonical one that will be matched by a single ADDSUB at ISel stage. The idea of converting a non-canonical ADDSUB into a canonical one by swapping the first two operands of the shuffle, and then negating the second operand of the FADD and FSUB, was originally proposed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211771 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch removed duplicate code for matching patterns Dinesh Dwivedi2014-06-26
| | | | | | | | | | | which are now handled in SimplifyUsingDistributiveLaws() (after r211261) Differential Revision: http://reviews.llvm.org/D4253 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211768 91177308-0d34-0410-b5e6-96231b3b80d8
* Added instruction combine to transform few more negative values addition to ↵Dinesh Dwivedi2014-06-26
| | | | | | | | | | | | | | subtraction (Part 2) This patch enables transforms for (x + (~(y | c) + 1) --> x - (y | c) if c is even Differential Revision: http://reviews.llvm.org/D4209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211765 91177308-0d34-0410-b5e6-96231b3b80d8
* GlobalOpt: Don't optimize thread_local for initializersDavid Majnemer2014-06-26
| | | | | | | | Folding a reference to a thread_local variable into another global variable's initializer is very problematic, there is no relocation that exists to represent such an access. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211762 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix vector FMAMatt Arsenault2014-06-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211757 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't build switch tables for dllimport and TLS variables in GEPsHans Wennborg2014-06-26
| | | | | | | This is a follow-up to r211331, which failed to notice that we were returning early from ValidLookupTableConstant for GEPs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211753 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Fix asm syntax for packed vcmpAdam Nemet2014-06-26
| | | | | | | | The *_alt defs for vcmp are used by the InstParser (the asm string in the main def is used by the InstPrinter) . The former was accepting vector registers as destination rather than mask registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211750 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Only fold the cmp into the select when both instructions are ↵Juergen Ributzka2014-06-25
| | | | | | | | | | | | in the same basic block. If the cmp is in a different basic block, then it is possible that not all operands of that compare have defined registers. This can happen when one of the operands to the cmp is a load and the load gets folded into the cmp. In this case FastISel will skip the load instruction and the vreg is never defined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211730 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "PR20038: DebugInfo: Inlined call sites where the caller has debug ↵David Blaikie2014-06-25
| | | | | | | | | | | info but the call itself has no debug location." This reverts commit r211723. Breaks the ASan/compiler-rt build... guess I didn't test very far at all :/. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211724 91177308-0d34-0410-b5e6-96231b3b80d8
* PR20038: DebugInfo: Inlined call sites where the caller has debug info but ↵David Blaikie2014-06-25
| | | | | | | | | | | | | | | | | | the call itself has no debug location. This situation does bad things when inlined, so I've fixed Clang not to produce inlinable call sites without locations when the caller has debug info (in the one case where I could find that this occurred). This updates the PR20038 test case to be what clang now produces, and readds the assertion that had to be removed due to this bug. I've also beefed up the debug info verifier to help diagnose these issues in the future, and I hope to add checks to the inliner to just assert-fail if it encounters this situation. If, in the future, we decide we have to cope with this situation, the right thing to do is probably to just remove all the DebugLocs from the inlined instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211723 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Rpass-missed and Rpass-analysis reports to the loop vectorizer. The ↵Tyler Nowicki2014-06-25
| | | | | | | | | remarks give the vector width of vectorized loops and a brief analysis of loops that fail to be vectorized. For example, an analysis will be generated for loops containing control flow that cannot be simplified to a select. The optimization remarks also give the debug location of expressions that cannot be vectorized, for example the location of an unvectorizable call. Reviewed by: Arnold Schwaighofer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211721 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Always prefer to lower a VECTOR_SHUFFLE into a BLENDI instead of SHUFP ↵Andrea Di Biagio2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (or VPERM2X128). This patch teaches method 'LowerVECTOR_SHUFFLE' to give higher precedence to the check for 'isBlendMask'; the idea is that, when possible, we should firstly check if a shuffle performs a blend, and in case, try to lower it into a BLENDI instead of selecting a SHUFP or (worse) a VPERM2X128. In general: - AVX VBLENDPS/D always have better latency and throughput than VPERM2F128; - BLENDPS/D instructions tend to always have better 'reciprocal throughput' than the equivalent SHUFPS/D; - Both BLENDPS/D and SHUFPS/D are often decoded into the same number of m-ops; however, a m-op obtained from a BLENDPS/D can be scheduled to more than one execution port. This patch: - Moves the check for 'isBlendMask' immediately before the check for 'isSHUFPMask' within method 'LowerVECTOR_SHUFFLE'; - Updates existing tests for sse/avx shuffle/blend instructions to verify that we select (v)blendps/d when possible (instead of (v)shufps/d or vperm2f128). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211720 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some test files for r211710.Eli Bendersky2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211711 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename loop unrolling and loop vectorizer metadata to have a common prefix.Eli Bendersky2014-06-25
| | | | | | | | | | | | | | | | | | | | | [LLVM part] These patches rename the loop unrolling and loop vectorizer metadata such that they have a common 'llvm.loop.' prefix. Metadata name changes: llvm.vectorizer.* => llvm.loop.vectorizer.* llvm.loopunroll.* => llvm.loop.unroll.* This was a suggestion from an earlier review (http://reviews.llvm.org/D4090) which added the loop unrolling metadata. Patch by Mark Heffernan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211710 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Fix bad interaction between with-calls mode and chained origin tracking.Evgeniy Stepanov2014-06-25
| | | | | | | | | | | Origin history should only be recorded for uninitialized values, because it is meaningless otherwise. This change moves __msan_chain_origin to the runtime library side and makes it conditional on the corresponding shadow value. Previous code was correct, but _very_ inefficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211700 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add intrinsics for the pshufd, pshuflw, and pshufhw instructions.Chandler Carruth2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211694 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply r211399, "Generate native unwind info on Win64" with a fix to ↵NAKAMURA Takumi2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | ignore SEH pseudo ops in X86 JIT emitter. -- This patch enables LLVM to emit Win64-native unwind info rather than DWARF CFI. It handles all corner cases (I hope), including stack realignment. Because the unwind info is not flexible enough to describe stack frames with a gap of unknown size in the middle, such as the one caused by stack realignment, I modified register spilling code to place all spills into the fixed frame slots, so that they can be accessed relative to the frame pointer. Patch by Vadim Chugunov! Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D4081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211691 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add target combine rule to select ADDSUB instructions from a build_vectorAndrea Di Biagio2014-06-25
| | | | | | | | | | | | | | | | | | | This patch teaches the backend how to combine a build_vector that implements an 'addsub' between packed float vectors into a sequence of vector add and vector sub followed by a VSELECT. The new VSELECT is expected to be lowered into a BLENDI. At ISel stage, the sequence 'vector add + vector sub + BLENDI' is pattern-matched against ISel patterns added at r211427 to select 'addsub' instructions. Added three more ISel patterns for ADDSUB. Added test sse3-avx-addsub-2.ll to verify that we correctly emit 'addsub' instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211679 91177308-0d34-0410-b5e6-96231b3b80d8
* [LICM] Don't create more than one copy of an instruction per loop exit block ↵Evgeniy Stepanov2014-06-25
| | | | | | | | | | | | | | | | | | | | | when sinking. Fixes exponential compilation complexity in PR19835, caused by LICM::sink not handling the following pattern well: f = op g e = op f, g d = op e c = op d, e b = op c a = op b, c When an instruction with N uses is sunk, each of its operands gets N new uses (all of them - phi nodes). In the example above, if a had 1 use, c would have 2, e would have 4, and g would have 8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211673 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another asserting method in the null streamer.Rafael Espindola2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211668 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a regression from r211653.Rafael Espindola2014-06-25
| | | | | | | The method was empty in the null streamer but I mistakenly replaced it with the aborting one in MCStreamer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211666 91177308-0d34-0410-b5e6-96231b3b80d8
* CodeGen/X86/pr20088.ll: Add -march=x86-64, or llc fails due to non-x86 ↵NAKAMURA Takumi2014-06-25
| | | | | | default target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211659 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Fold XALU condition into branch and compare.Juergen Ributzka2014-06-24
| | | | | | | Optimize the codegen of select and branch instructions to directly use the EFLAGS from the {s|u}{add|sub|mul}.with.overflow intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211645 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-24
| | | | | | Now we need only one 64-bit pattern for stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211643 91177308-0d34-0410-b5e6-96231b3b80d8
* ldr-pseudo-obj-errors.s: Fix silly copypasto.NAKAMURA Takumi2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211642 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/MC/AArch64/ldr-pseudo-obj-errors.s: Add -triple=aarch64-linux. ↵NAKAMURA Takumi2014-06-24
| | | | | | | | AArch64 is unaware of PECOFF for now. FIXME: This should pass for also targeting aarch64-darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211640 91177308-0d34-0410-b5e6-96231b3b80d8
* Print a=b as an assignment.Rafael Espindola2014-06-24
| | | | | | | | | | | In assembly the expression a=b is parsed as an assignment, so it should be printed as one. This remove a truly horrible hack for producing a label with "a=.". It would be used by codegen but would never be reached by the asm parser. Sorry I missed this when it was first committed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211639 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-24
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211637 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up scoping in a few tests (and delete one that validates unnecessary ↵David Blaikie2014-06-24
| | | | | | | | | | | | | | | | behavior). Most of this is just tests that were silently succeeding in spite of schema changes I made over a year ago. Cleaning them up as they lead to failures in a change I'm working on/will come soon. test/DebugInfo/2010-01-19-DbgScope.ll was removed as it tested miscoping where a DebugLoc described a location not in the current function. The test case doesn't describe why this is a valid situation and should be supported, so I'm removing it and shortly going to commit changes that make this firmly unsupported/assert-fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211628 91177308-0d34-0410-b5e6-96231b3b80d8
* [PPC64] Fix PR20071 (fctiduz generated for targets lacking that instruction)Bill Schmidt2014-06-24
| | | | | | | | | | | | | | | | | | PR20071 identifies a problem in PowerPC's fast-isel implementation for floating-point conversion to integer. The fctiduz instruction was added in Power ISA 2.06 (i.e., Power7 and later). However, this instruction is being generated regardless of which 64-bit PowerPC target is selected. The intent is for fast-isel to punt to DAG selection when this instruction is not available. This patch implements that change. For testing purposes, the existing fast-isel-conversion.ll test adds a RUN line for -mcpu=970 and tests for the expected code generation. Additionally, the existing test fast-isel-conversion-p5.ll was found to be incorrectly expecting the unavailable instruction to be generated. I've removed these test variants since we have adequate coverage in fast-isel-conversion.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211627 91177308-0d34-0410-b5e6-96231b3b80d8
* vpblend intrinsics combines as shifts intrinsics due to absence return stmt ↵Robert Khasanov2014-06-24
| | | | | | | | | | | between them Fix PR20088 Differential Revision: http://reviews.llvm.org/D4277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211617 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test case in r211605/r211533Weiming Zhao2014-06-24
| | | | | | | | | The test case in "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" should only work with Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211613 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new debug kind LocTrackingOnly.Diego Novillo2014-06-24
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This new debug emission kind supports emitting line location information in all instructions, but stops code generation from emitting debug info to the final output. This mode is useful when the backend wants to track source locations during code generation, but it does not want to produce debug info. This is currently used by optimization remarks (-pass-remarks, -pass-remarks-missed and -pass-remarks-analysis). To prevent debug info emission, DIBuilder never inserts the annotation 'llvm.dbg.cu' when LocTrackingOnly is enabled. Reviewers: echristo, dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4234 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211609 91177308-0d34-0410-b5e6-96231b3b80d8
* Resubmit commit r211533Weiming Zhao2014-06-24
| | | | | | | | | "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Missed files are added in this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211605 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix TPsoft for Thumb modeChristian Pirker2014-06-24
| | | | | | | | Reviewed at http://reviews.llvm.org/D4230 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211601 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Added support for assembling sdbbp.Daniel Sanders2014-06-24
| | | | | | | | | | | Summary: This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too. Differential Revision: http://reviews.llvm.org/D4265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211590 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Disable umul.with.overflow recognition for vectors.Benjamin Kramer2014-06-24
| | | | | | It doesn't make a lot on most targets and the code isn't ready for it. PR20113. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211583 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Don't try to reorder shuffles where the mask is a ConstantExpr.Benjamin Kramer2014-06-24
| | | | | | We can't analyze the individual values of a vector expression. PR20114. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211581 91177308-0d34-0410-b5e6-96231b3b80d8
* GlobalOpt: Don't optimize dllimport for initializersDavid Majnemer2014-06-24
| | | | | | | | | Referencing a dllimport variable requires actually instructions, not just a relocation. This fixes PR19955. Differential Revision: http://reviews.llvm.org/D4249 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211571 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix a build_vector pattern match failKevin Qin2014-06-24
| | | | | | caused by defect in isBuildVectorAllZeros(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211567 91177308-0d34-0410-b5e6-96231b3b80d8
* [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fieldsAdam Nemet2014-06-24
| | | | | | | | | V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and NDS register fields. This was simply not used in the decoder until now. Fixes <rdar://problem/17402661> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211565 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Lower unsupported selects to control-flow.Juergen Ributzka2014-06-23
| | | | | | | | The extends the select lowering coverage by emiting pseudo cmov instructions. These insturction will be later on lowered to control-flow to simulate the select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211545 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Add support for floating-point select.Juergen Ributzka2014-06-23
| | | | | | | | | | This extends the select lowering to support floating-point selects. The lowering depends on SSE instructions and that the conditon comes from a floating-point compare. Under this conditions it is possible to emit an optimized instruction sequence that doesn't require any branches to simulate the select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211544 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Optimize selects when the condition comes from a compare.Juergen Ributzka2014-06-23
| | | | | | | Optimize the select instructions sequence to use the EFLAGS directly from a compare when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211543 91177308-0d34-0410-b5e6-96231b3b80d8
* nm-trivial-object.test requires shell since Lit internal runner isn't ↵NAKAMURA Takumi2014-06-23
| | | | | | capable of chdir. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211537 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the default input for llvm-nm to be a.out instead of standard inputKevin Enderby2014-06-23
| | | | | | | | | | to match llvm-size and other UNIX systems for their nm(1). Tweak test cases that used llvm-nm with standard input to add a "-" to indicate that and add a test case to check the default of a.out for llvm-nm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211529 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] Add a target streamer when creating a null streamer.Rafael Espindola2014-06-23
| | | | | | Should fix DebugInfo/global.ll on the mips bot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211527 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-23
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211523 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMEB: Vector extend operationsChristian Pirker2014-06-23
| | | | | | | | Reviewed at http://reviews.llvm.org/D4043 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211520 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-23
| | | | | | Add more tests for these. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211517 91177308-0d34-0410-b5e6-96231b3b80d8
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