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path: root/utils/TableGen/CodeGenInstruction.h
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* Add back in r109901, which adds a Compare flag to the target instructions. It'sBill Wendling2010-08-08
| | | | | | | useful after all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn'tBill Wendling2010-08-06
| | | | | | | | | | | | | | | need the Compare flag after all. --- Reverse-merging r109901 into '.': U include/llvm/Target/TargetInstrDesc.h U include/llvm/Target/Target.td U utils/TableGen/InstrInfoEmitter.cpp U utils/TableGen/CodeGenInstruction.cpp U utils/TableGen/CodeGenInstruction.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110424 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a "Compare" flag to the target instruction descriptor. This will be usedBill Wendling2010-07-30
| | | | | | | | later to identify and possibly remove superfluous compare instructions -- those that are testing for and setting a status flag that should already be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
* hoist some funky logic into CodeGenInstructionChris Lattner2010-03-27
| | | | | | | | | | from two places in CodeGenDAGPatterns.cpp, and use it in DAGISelMatcherGen.cpp instead of using an incorrect predicate that happened to get lucky on our current targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99726 91177308-0d34-0410-b5e6-96231b3b80d8
* capture implicit uses and defs in CodeGenInstructionChris Lattner2010-03-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98879 91177308-0d34-0410-b5e6-96231b3b80d8
* remove some code that was working around old sparc v9 backend bugs.Chris Lattner2010-03-18
| | | | | | | Add checking that the input/output operand list in spelled right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98865 91177308-0d34-0410-b5e6-96231b3b80d8
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
* work around a gcc bug with -Wuninitialized.Chris Lattner2010-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95808 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce a new CodeGenInstruction::ConstraintInfo classChris Lattner2010-02-10
| | | | | | | | | | for representing constraint info semantically instead of as a c expression that will be blatted out to the .inc file. Fix X86RecognizableInstr to use this instead of parsing C code :). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95753 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-29
| | | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. WhenEvan Cheng2009-10-01
| | | | | | | | | | | set, these flags indicate the instructions source / def operands have special register allocation requirement that are not captured in their register classes. Post-allocation passes (e.g. post-alloc scheduler) should not change their allocations. e.g. ARM::LDRD require the two definitions to be allocated even / odd register pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling2008-05-28
| | | | | | | | | | instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-10
| | | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
* add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner2008-01-08
| | | | | | | This is currently not set by anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45748 91177308-0d34-0410-b5e6-96231b3b80d8
* rename hasVariableOperands() -> isVariadic(). Add some comments.Chris Lattner2008-01-07
| | | | | | | | Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8
* the name field of instructions is never set to a non-empty string, Chris Lattner2008-01-07
| | | | | | | just unconditionally use the def name of the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45684 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the impl of CodeGenInstruction out to its own .cpp file, add a ↵Chris Lattner2008-01-06
| | | | | | getName() accessor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45645 91177308-0d34-0410-b5e6-96231b3b80d8
* remove attributions from utils.Chris Lattner2007-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-14
| | | | | | | side effects for machine instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45022 91177308-0d34-0410-b5e6-96231b3b80d8
* Oops. Forgot these.Evan Cheng2007-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44969 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag for indirect branch instructions.Owen Anderson2007-11-12
| | | | | | | Target maintainers: please check that the instructions for your target are correctly marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
* No need for noResults anymore.Evan Cheng2007-07-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40075 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-19
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* Try committing again. Add OptionalDefOperand. Remove clobbersPred.Evan Cheng2007-07-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38498 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-26
| | | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-19
| | | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
* Add clobbersPred - instruction that clobbers condition code / register which ↵Evan Cheng2007-06-06
| | | | | | are used to predicate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable ↵Evan Cheng2007-05-16
| | | | | | without having a PredicateOperand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37116 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize target instruction flag 'isReMaterializable'.Evan Cheng2007-03-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35159 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the isTwoAddress property from the CodeGenInstruction class. It shouldChris Lattner2006-11-15
| | | | | | | | | | | not be used for anything other than backwards compat constraint handling. Add support for a new DisableEncoding property which contains a list of registers that should not be encoded by the generated code emitter. Convert the codeemitter generator to use this, fixing some PPC JIT regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31769 91177308-0d34-0410-b5e6-96231b3b80d8
* ADd support for adding constraints to suboperandsChris Lattner2006-11-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31748 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify the way operand flags and constraints are handled, making it easierChris Lattner2006-11-06
| | | | | | | to extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31481 91177308-0d34-0410-b5e6-96231b3b80d8
* recognize ppc's blr instruction as predicatedChris Lattner2006-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31480 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak VC++ build.Jeff Cohen2006-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31464 91177308-0d34-0410-b5e6-96231b3b80d8
* Add operand constraints to TargetInstrInfo.Evan Cheng2006-11-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31333 91177308-0d34-0410-b5e6-96231b3b80d8
* * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag andEvan Cheng2006-01-09
| | | | | | | | | | SNDPOutFlag to DAG nodes. These properties do not belong to target specific instructions. * Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's optional. Used by ret / call, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25154 91177308-0d34-0410-b5e6-96231b3b80d8
* Added field noResults to Instruction.Evan Cheng2005-12-26
| | | | | | | | | | | | | Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
* * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAGEvan Cheng2005-12-23
| | | | | | | | support which is fragile. * Fixed a number of bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24996 91177308-0d34-0410-b5e6-96231b3b80d8
* * Commit the fix (by Chris) for a tblgen type inferencing bug.Evan Cheng2005-12-04
| | | | | | | | | | | | * Enhanced tblgen to handle instructions which have chain operand and writes a chain result. * Enhanced tblgen to handle instructions which produces no results. Part of the change is a temporary hack which relies on instruction property (e.g. isReturn, isBranch). The proper fix would be to change the .td syntax to separate results dag from ops dag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24587 91177308-0d34-0410-b5e6-96231b3b80d8
* Nuke CodeGenInstruction's ValueType member, it is no longer used.Nate Begeman2005-12-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24556 91177308-0d34-0410-b5e6-96231b3b80d8
* fit into 80 columnsNate Begeman2005-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24554 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach tblgen about instruction operands that have multiple MachineInstrChris Lattner2005-11-19
| | | | | | | | operands, digging into them to find register values (used on X86). Patch by Evan Cheng! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24424 91177308-0d34-0410-b5e6-96231b3b80d8
* spell this variable rightChris Lattner2005-08-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23095 91177308-0d34-0410-b5e6-96231b3b80d8
* Expose a new flag to TargetInstrInfoChris Lattner2005-08-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23094 91177308-0d34-0410-b5e6-96231b3b80d8
* For now, just emit empty operand info structures.Chris Lattner2005-08-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22910 91177308-0d34-0410-b5e6-96231b3b80d8
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