summaryrefslogtreecommitdiff
path: root/utils/TableGen
Commit message (Collapse)AuthorAge
* Use the correct comparator to avoid depending on pointer values.Jakob Stoklund Olesen2011-06-18
| | | | | | This should fix the Linux buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133334 91177308-0d34-0410-b5e6-96231b3b80d8
* Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen2011-06-18
| | | | | | | Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove MethodProtos/MethodBodies and allocation_order_begin/end.Jakob Stoklund Olesen2011-06-18
| | | | | | | | | | | | | | Targets that need to change the default allocation order should use the AltOrders mechanism instead. See the X86 and ARM targets for examples. The allocation_order_begin() and allocation_order_end() methods have been replaced with getRawAllocationOrder(), and there is further support functions in RegisterClassInfo. It is no longer possible to insert arbitrary code into generated register classes. This is a feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide AltOrders for specifying alternative allocation orders.Jakob Stoklund Olesen2011-06-18
| | | | | | | | | | | | A register class can define AltOrders and AltOrderSelect instead of defining method protos and bodies. The AltOrders lists can be defined with set operations, and TableGen can verify that the alternative allocation orders only contain valid registers. This is currently an opt-in feature, and it is still possible to override allocation_order_begin/end. That will not be true for long. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix formatting.Owen Anderson2011-06-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133164 91177308-0d34-0410-b5e6-96231b3b80d8
* Prempt some obnoxious compiler from complaing about signed/unsignedJakob Stoklund Olesen2011-06-16
| | | | | | | | | compares. 2^30 is actually the limit on the number of physical registers per TargetRegisterInfo.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133142 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to pass an unsigned to a printf format that is always %u.Jakob Stoklund Olesen2011-06-16
| | | | | | This should unbreak the native ARM testers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133141 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new MVT::untyped. This will be used in future work for modelling ISA ↵Owen Anderson2011-06-15
| | | | | | features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133106 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the Clang diagnostic emitter to emit IDs for diagnostic categories.John McCall2011-06-15
| | | | | | | | Patch by Argyrios Kyrtzidis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133093 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the statically generated hashtables for checking register ↵Owen Anderson2011-06-15
| | | | | | | | | | relationships with just scanning the (typically tiny) static lists. At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries. Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan. With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time. It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133051 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a SetTheory instance to expand register lists in register classes.Jakob Stoklund Olesen2011-06-15
| | | | | | | | This prepares tablegen to compute register lists from set theoretic dag expressions. This doesn't really make any difference as long as Target.td still declares RegisterClass::MemberList as [Register]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133043 91177308-0d34-0410-b5e6-96231b3b80d8
* Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen2011-06-15
| | | | | | | | | | | Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the heuristic to emit the alias if the number of hard-coded registersBill Wendling2011-06-15
| | | | | | | are also greater than the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the list of register classes into CodeGenRegBank as well.Jakob Stoklund Olesen2011-06-15
| | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133029 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a compile time regression caused by too small hash tables.Jakob Stoklund Olesen2011-06-14
| | | | | | | | | | | | | | Measure the worst case number of probes for a miss instead of the less conservative number of probes required for an insertion. Lower the limit to < 6 probes worst case. This doubles the size of the ARM and X86 hash tables, other targets are unaffected. LiveVariables runs 12% faster with this change. <rdar://problem/9598545> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132999 91177308-0d34-0410-b5e6-96231b3b80d8
* Heuristic: If the number of operands in the alias are more than the number ofBill Wendling2011-06-14
| | | | | | | operands in the aliasee, don't print the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak hash function and compress hash tables.Jakob Stoklund Olesen2011-06-12
| | | | | | | | | | | | | | | | | Make the hash tables as small as possible while ensuring that all lookups can be done in less than 8 probes. Cut the aliases hash table in half by only storing a < b pairs - it is a symmetric relation. Use larger multipliers on the initial hash function to ensure that it properly covers the whole table, and to resolve some clustering in the very regular ARM register bank. This reduces the size of most of these tables by 4x - 8x. For instance, the ARM tables shrink from 48 KB to 8 KB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132888 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove now dead code.Jakob Stoklund Olesen2011-06-12
| | | | | | These computations have been moved to CodeGenRegisters.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132887 91177308-0d34-0410-b5e6-96231b3b80d8
* Extract the generateHashTable function.Jakob Stoklund Olesen2011-06-12
| | | | | | | | | | | The constant hash tables for sub-registers and overlaps are generated the same way, so extract a function to generate and print the hash table. Also use the information computed by CodeGenRegisters.cpp instead of the locally data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132886 91177308-0d34-0410-b5e6-96231b3b80d8
* Compute lists of sub-regs, super-regs, and overlapping regs.Jakob Stoklund Olesen2011-06-12
| | | | | | | | | | | | | | | | | | | | | | | Besides moving structural computations to CodeGenRegisters.cpp, this also well-defines the order of these lists: - Sub-register lists come from a pre-order traversal of the graph defined by the SubRegs lists in the .td files. - Super-register lists are topologically ordered so no register comes before any of its sub-registers. When the sub-register graph is not a tree, independent super-registers appear in numerical order. - Lists of overlapping registers are ordered according to register number. This reverses the order of the super-regs lists, but nobody was depending on that. The previous order of the overlaps lists was odd, and it may have depended on the precise behavior of std::stable_sort. The old computations are still there, but will be removed shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen2011-06-11
| | | | | | | Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen2011-06-10
| | | | | | | Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TableGen's register bank classes to their own source file.Jakob Stoklund Olesen2011-06-09
| | | | | | | | | | | I'll be moving some more code there to gather all of the register-specific stuff in one place. Currently it is shared between CodeGenTarget and RegisterInfoEmitter. The plan is that CodeGenRegisters can compute the full register bank structure while RegisterInfoEmitter only will handle the printing part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
* Add special-case range checking for VCVT_N intrinsic immediate operands.Bob Wilson2011-06-09
| | | | | | Radar 9558930. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132782 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a few illegal paths with llvm_unreachable. Patch by Cameron McInally.Chad Rosier2011-06-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132732 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop a RecordKeeper reference that wasn't necessary.Jakob Stoklund Olesen2011-06-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132636 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence compiler warnings.Jakob Stoklund Olesen2011-06-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132624 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach TableGen to evaluate DAG expressions as set operations.Jakob Stoklund Olesen2011-06-04
| | | | | | | | | | | | | | | | | A TableGen backend can define how certain classes can be expanded into ordered sets of defs, typically by evaluating a specific field in the record. The SetTheory class can then evaluate DAG expressions that refer to these named sets. A number of standard set and list operations are predefined, and the backend can add more specialized operators if needed. The -print-sets backend is used by SetTheory.td to provide examples. This is intended to simplify how register classes are defined: def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132621 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework the logic to not rely on undefined behaviour (1LL << 64). Also simplify.Nick Lewycky2011-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132537 91177308-0d34-0410-b5e6-96231b3b80d8
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-02
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new -d option to tblgen. It writes a make(1)-style dependency file.Joerg Sonnenberger2011-06-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132395 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes2011-05-31
| | | | | | | must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-30
| | | | | | | | directives. Fixes PR9826. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce the DwarfRegAlias class for declaring that two registers have theRafael Espindola2011-05-30
| | | | | | | | | | same dwarf number. This will be used for creating a dwarf number to register mapping. The only case that needs this so far is the XMM/YMM registers that unfortunately do have the same numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
* Change how tblgen generates attributes for intrinsics to use a singleJohn McCall2011-05-28
| | | | | | | | | | | switch. With this newfound organization, teach tblgen how not to give all intrinsics the 'nounwind' attribute. Introduce a new intrinsic, llvm.eh.resume, which does not have this attribute. Documentation and uses to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132252 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the root cause of the bootstrap failure:Rafael Espindola2011-05-28
| | | | | | | | There was no way to check if a given register/mode pair was valid. We now return an error code (-2) instead of asserting. If anyone thinks that an assert at this point is really needed, we can autogen a hasValidDwarfRegNum instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132236 91177308-0d34-0410-b5e6-96231b3b80d8
* [tablegen] A couple of changes to ClangDiagnosticEmmitter.Argyrios Kyrtzidis2011-05-25
| | | | | | | | -Emit an empty warning option as string ("") instead of 0. -For diagnostic names also emit the size of the string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132046 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a more efficient data structure for the "operand map". The number ofBill Wendling2011-05-23
| | | | | | | | operands to an instruction aren't great, so an iterative search is fairly quick and doesn't have the overhead of std::map. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131886 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR9947 by placing OPFL_MemRefs on the node using memory operands rather thanCameron Zwarich2011-05-19
| | | | | | | the root if there is only one such node. This leaves only 2 verifier failures in the entire test suite when running "make check". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131677 91177308-0d34-0410-b5e6-96231b3b80d8
* Downgrade a tablegen warning to an error.Jakob Stoklund Olesen2011-05-10
| | | | | | | Ambiguous sub-register index compositions are OK as long as the backend writer knows what he is doing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131134 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed MC encoding for index_align for VLD1/VST1 (single element from one ↵Mon P Wang2011-05-09
| | | | | | lane) for size 32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach TableGen to automatically generate missing SubRegIndex instances.Jakob Stoklund Olesen2011-05-07
| | | | | | | The RegisterInfo.td file should only specify the indexes that sources need to refer to. The rest is inferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131058 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve diagnostics for some parse errors. Not asserting when a user inputJim Grosbach2011-05-06
| | | | | | error is detected is a good thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131005 91177308-0d34-0410-b5e6-96231b3b80d8
* ParseFile() may throw, so extend the try/catch to handle that.Jim Grosbach2011-05-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131004 91177308-0d34-0410-b5e6-96231b3b80d8
* llvmc: Make it possible to provide an argument to (join).Mikhail Glushenkov2011-05-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130914 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Add missing newline to generated file.Jim Grosbach2011-05-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130779 91177308-0d34-0410-b5e6-96231b3b80d8
* Filter out pattterns from the FastISel emitter which it doesn't actually ↵Eli Friedman2011-04-29
| | | | | | know how to handle. No significant functionality change at the moment, but it's necessary for some changes I'm planning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130547 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in tblgen that caused incorrect encodings on instructions that ↵Owen Anderson2011-04-28
| | | | | | | | | | specified operands with "bit" instead of "bits<1>". Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question. <rdar://problem/9345702> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130410 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a TODO.Mikhail Glushenkov2011-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130092 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused STL header includes.Jay Foad2011-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130068 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-15 15:28:22 +0000