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* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
* Use array_lengthofJoerg Sonnenberger2011-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128823 91177308-0d34-0410-b5e6-96231b3b80d8
* Change loops to derive the number of tables automaticallyJoerg Sonnenberger2011-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128818 91177308-0d34-0410-b5e6-96231b3b80d8
* tlbgen/MC: StringRef's to temporary objects considered harmful.Daniel Dunbar2011-04-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128735 91177308-0d34-0410-b5e6-96231b3b80d8
* Add annotations to tablegen-generated processor itineraries, or replace them ↵Andrew Trick2011-04-01
| | | | | | with something meaningful. I want to be able to read and debug the generated tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128703 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-04-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128701 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in generated HTML.Nick Lewycky2011-03-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128594 91177308-0d34-0410-b5e6-96231b3b80d8
* Use intrinsics for Neon vmull operations. Radar 9208957.Bob Wilson2011-03-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128591 91177308-0d34-0410-b5e6-96231b3b80d8
* ClangSAEmClangSACheckersEmitter, emit info about groups.Argyrios Kyrtzidis2011-03-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128515 91177308-0d34-0410-b5e6-96231b3b80d8
* Quiet a gcc warning about changed name lookup rulesMatt Beaumont-Gay2011-03-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128497 91177308-0d34-0410-b5e6-96231b3b80d8
* In ClangSACheckersEmitter:Argyrios Kyrtzidis2011-03-29
| | | | | | | | - Also emit a list of packages and groups sorted by name - Avoid iterating over DenseSet so that the output of the arrays is deterministic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128489 91177308-0d34-0410-b5e6-96231b3b80d8
* For ClangSACheckersEmitter, allow a package to belong to checker group, in ↵Argyrios Kyrtzidis2011-03-29
| | | | | | which all its checkers will go into the group. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128474 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove scripts used by TEST=dbg from here. They now live inside llvm test suite.Devang Patel2011-03-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128425 91177308-0d34-0410-b5e6-96231b3b80d8
* Partially revert commit 127155: I think it is much more convenientDuncan Sands2011-03-27
| | | | | | | | to have structured log files rather than one big file produced by piping output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128378 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend Clang's TableGen emitter for attributes to support bool arguments.Douglas Gregor2011-03-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128330 91177308-0d34-0410-b5e6-96231b3b80d8
* Useful script for finding regressions in the nightly testsuite.Duncan Sands2011-03-25
| | | | | | | I think it was written by Pawel Worach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128268 91177308-0d34-0410-b5e6-96231b3b80d8
* delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ↵Johnny Chen2011-03-25
| | | | | | instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
* The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ↵Johnny Chen2011-03-24
| | | | | | | | | | stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen2011-03-24
| | | | | | | | According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-24
| | | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the Clang attribute emitter to handle attributes of 'version'Douglas Gregor2011-03-23
| | | | | | | | kind, and fix serialization/deserialization of IdentifierInfo attributes. These are requires for the new 'availability' attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128130 91177308-0d34-0410-b5e6-96231b3b80d8
* Call static functions so that they aren't left unused.Bill Wendling2011-03-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128020 91177308-0d34-0410-b5e6-96231b3b80d8
* A WIP commit of the InstAlias printing cleanup. This code will soon replace theBill Wendling2011-03-21
| | | | | | | | code below it. Even though it looks very similar, it will match more precisely and geneate better functions in the long run. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127991 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the IAPrinter class.Bill Wendling2011-03-21
| | | | | | | | This is a helper class that will make it easier to say which InstAliases can be printed and which cannot (because of ambiguity). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127990 91177308-0d34-0410-b5e6-96231b3b80d8
* * Add classes that support the "feature" information.Bill Wendling2011-03-21
| | | | | | | * Move the code that emits the reg in reg class matching into its own function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127988 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson2011-03-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127888 91177308-0d34-0410-b5e6-96231b3b80d8
* raw_ostream: [PR6745] Tweak formatting (double)%e for Windows hosts.NAKAMURA Takumi2011-03-18
| | | | | | | | On MSVCRT and compatible, output of %e is incompatible to Posix by default. Number of exponent digits should be at least 2. "%+03d" FIXME: Implement our formatter in future! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127872 91177308-0d34-0410-b5e6-96231b3b80d8
* lit/ProgressBar.py: [PR7919] Improve line wrap for XN-incapable terminals.NAKAMURA Takumi2011-03-15
| | | | | | On Win32 console, emitting char to col#79 causes linefeed, and the cursor will not return to col#79 upper line with backspace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127696 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add "Bitcast" target instruction property for instructions which performEvan Cheng2011-03-15
| | | | | | | | nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-15
| | | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
* Ignore isCodeGenOnly instructions when generating diassembly tables.Owen Anderson2011-03-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127619 91177308-0d34-0410-b5e6-96231b3b80d8
* Trailing whitespace.Jim Grosbach2011-03-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127592 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct small comment order typo.Francois Pichet2011-03-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127575 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove no-longer-correct special case for disasm of ARM BL instructions.Jim Grosbach2011-03-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127517 91177308-0d34-0410-b5e6-96231b3b80d8
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127508 91177308-0d34-0410-b5e6-96231b3b80d8
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127491 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach2011-03-11
| | | | | | as for VDUP32d and VDUP32q, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127488 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-11
| | | | | | and VDUPLN32d, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach2011-03-11
| | | | | | as for VREV64d32 and VREV64q32, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing 'return on failure'. Previously we'd crash after emittingJim Grosbach2011-03-11
| | | | | | the diagnostic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127480 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach TableGen to pre-calculate register enum values when creating theJim Grosbach2011-03-11
| | | | | | | | | | | | | CodeGenRegister entries. Use this information to more intelligently build the literal register entires in the DAGISel matcher table. Specifically, use a single-byte OPC_EmitRegister entry for registers with a value of less than 256 and OPC_EmitRegister2 entry for registers with a larger value. rdar://9066491 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127456 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the register enum value part of the CodeGenRegister struct.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
* Trailing whitespace.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127447 91177308-0d34-0410-b5e6-96231b3b80d8
* Trailing whitespace.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127446 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127445 91177308-0d34-0410-b5e6-96231b3b80d8
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