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|
//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//
// ARM Instruction Format Definitions.
//
// Format specifies the encoding used by the instruction. This is part of the
// ad-hoc solution used to emit machine instruction encodings by our machine
// code emitter.
class Format<bits<5> val> {
bits<5> Value = val;
}
def Pseudo : Format<1>;
def MulFrm : Format<2>;
def MulSMLAW : Format<3>;
def MulSMULW : Format<4>;
def MulSMLA : Format<5>;
def MulSMUL : Format<6>;
def Branch : Format<7>;
def BranchMisc : Format<8>;
def UnaryFrm : Format<9>;
def BinaryFrm : Format<10>;
def LdFrm : Format<11>;
def StFrm : Format<12>;
def ArithMisc : Format<13>;
def ThumbFrm : Format<14>;
def VFPFrm : Format<15>;
//===----------------------------------------------------------------------===//
// ARM Instruction templates.
//
class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
Format f, string cstr>
: Instruction {
field bits<32> Inst;
let Namespace = "ARM";
bits<4> Opcode = opcod;
AddrMode AM = am;
bits<4> AddrModeBits = AM.Value;
SizeFlagVal SZ = sz;
bits<3> SizeFlag = SZ.Value;
IndexMode IM = im;
bits<2> IndexModeBits = IM.Value;
Format F = f;
bits<5> Form = F.Value;
let Constraints = cstr;
}
class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
: InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
let OutOperandList = oops;
let InOperandList = iops;
let AsmString = asm;
let Pattern = pattern;
}
// Almost all ARM instructions are predicable.
class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, string opc, string asm, string cstr,
list<dag> pattern>
: InstARM<opcod, am, sz, im, f, cstr> {
let OutOperandList = oops;
let InOperandList = !con(iops, (ops pred:$p));
let AsmString = !strconcat(opc, !strconcat("${p}", asm));
let Pattern = pattern;
list<Predicate> Predicates = [IsARM];
}
// Same as I except it can optionally modify CPSR. Note it's modeled as
// an input operand since by default it's a zero register. It will
// become an implicit def once it's "flipped".
class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, string opc, string asm, string cstr,
list<dag> pattern>
: InstARM<opcod, am, sz, im, f, cstr> {
let OutOperandList = oops;
let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
let Pattern = pattern;
list<Predicate> Predicates = [IsARM];
}
// Special cases
class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
: InstARM<opcod, am, sz, im, f, cstr> {
let OutOperandList = oops;
let InOperandList = iops;
let AsmString = asm;
let Pattern = pattern;
list<Predicate> Predicates = [IsARM];
}
class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
asm,"",pattern>;
class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
asm,"",pattern>;
class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
"", pattern>;
// Ctrl flow instructions
class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
asm,"",pattern> {
let Inst{24} = 1; // L bit
let Inst{25-27} = 5;
}
class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{24} = 1; // L bit
let Inst{25-27} = 5;
}
class ABLXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{4-7} = 3;
let Inst{20-27} = 0x12;
}
// FIXME: BX
class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
"", pattern>;
class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{24} = 0; // L bit
let Inst{25-27} = 5;
}
class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
asm,"",pattern> {
let Inst{24} = 0; // L bit
let Inst{25-27} = 5;
}
// BR_JT instructions
// == mov pc
class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
asm, "", pattern> {
let Inst{20} = 0; // S Bit
let Inst{21-24} = 0xd;
let Inst{26-27} = 0;
}
// == ldr pc
class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
asm, "", pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
// == add pc
class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
asm, "", pattern> {
let Inst{20} = 0; // S bit
let Inst{21-24} = 4;
let Inst{26-27} = 0;
}
// addrmode1 instructions
class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{21-24} = opcod;
let Inst{26-27} = 0;
}
class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{21-24} = opcod;
let Inst{26-27} = 0;
}
class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{21-24} = opcod;
let Inst{26-27} = 0;
}
class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
asm, "", pattern>;
// addrmode2 loads and stores
class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{26-27} = 1;
}
class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
"", pattern>;
// loads
class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
// stores
class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
// Pre-indexed loads
class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
// Pre-indexed stores
class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
// Post-indexed loads
class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 0; // P bit
}
class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit
}
// Post-indexed stores
class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 0; // P bit
}
class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit
}
// addrmode3 instructions
class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern>;
class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
"", pattern>;
// loads
class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 0; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{4} = 1;
let Inst{5} = 0; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 0; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
// stores
class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
// Pre-indexed loads
class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit
}
class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit
}
class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{4} = 1;
let Inst{5} = 0; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit
}
// Pre-indexed stores
class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit
}
// Post-indexed loads
class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit
}
class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit
}
class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{4} = 1;
let Inst{5} = 0; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit
}
// Post-indexed stores
class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit
}
// addrmode4 instructions
class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{25-27} = 0x4;
}
class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 1; // L bit
let Inst{22} = 0; // S bit
let Inst{25-27} = 0x4;
}
class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 1; // L bit
let Inst{22} = 1; // S bit
let Inst{25-27} = 0x4;
}
class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 0; // L bit
let Inst{22} = 0; // S bit
let Inst{25-27} = 0x4;
}
//===----------------------------------------------------------------------===//
// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsARM];
}
class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsARM, HasV5TE];
}
class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsARM, HasV6];
}
//===----------------------------------------------------------------------===//
//
// Thumb Instruction Format Definitions.
//
// TI - Thumb instruction.
class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
string asm, string cstr, list<dag> pattern>
// FIXME: Set all opcodes to 0 for now.
: InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
let OutOperandList = outs;
let InOperandList = ins;
let AsmString = asm;
let Pattern = pattern;
list<Predicate> Predicates = [IsThumb];
}
class TI<dag outs, dag ins, string asm, list<dag> pattern>
: ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
class TI1<dag outs, dag ins, string asm, list<dag> pattern>
: ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
class TI2<dag outs, dag ins, string asm, list<dag> pattern>
: ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
class TI4<dag outs, dag ins, string asm, list<dag> pattern>
: ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
class TIs<dag outs, dag ins, string asm, list<dag> pattern>
: ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
// Two-address instructions
class TIt<dag outs, dag ins, string asm, list<dag> pattern>
: ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
// BL, BLX(1) are translated by assembler into two instructions
class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
: ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
// BR_JT instructions
class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
: ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
//===----------------------------------------------------------------------===//
// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsThumb];
}
class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsThumb, HasV5T];
}
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