1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
|
//===- SPURegisterInfo.h - Cell SPU Register Information Impl ----*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Cell SPU implementation of the TargetRegisterInfo
// class.
//
//===----------------------------------------------------------------------===//
#ifndef SPU_REGISTERINFO_H
#define SPU_REGISTERINFO_H
#include "SPU.h"
#include "SPUGenRegisterInfo.h.inc"
namespace llvm {
class SPUSubtarget;
class TargetInstrInfo;
class Type;
class SPURegisterInfo : public SPUGenRegisterInfo {
private:
const SPUSubtarget &Subtarget;
const TargetInstrInfo &TII;
//! Predicate: Does the machine function use the link register?
bool usesLR(MachineFunction &MF) const;
public:
SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
//! Translate a register's enum value to a register number
/*!
This method translates a register's enum value to it's regiser number,
e.g. SPU::R14 -> 14.
*/
static unsigned getRegisterNumbering(unsigned RegEnum);
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
virtual const TargetRegisterClass *
getPointerRegClass(unsigned Kind = 0) const;
/// After allocating this many registers, the allocator should feel
/// register pressure. The value is a somewhat random guess, based on the
/// number of non callee saved registers in the C calling convention.
virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
MachineFunction &MF) const{
return 50;
}
//! Return the array of callee-saved registers
virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
//! Allow for scavenging, so we can get scratch registers when needed.
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
{ return true; }
//! Return the reserved registers
BitVector getReservedRegs(const MachineFunction &MF) const;
//! Eliminate the call frame setup pseudo-instructions
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
//! Convert frame indicies into machine operands
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
RegScavenger *RS = NULL) const;
//! Get return address register (LR, aka R0)
unsigned getRARegister() const;
//! Get the stack frame register (SP, aka R1)
unsigned getFrameRegister(const MachineFunction &MF) const;
//------------------------------------------------------------------------
// New methods added:
//------------------------------------------------------------------------
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
//! Convert D-form load/store to X-form load/store
/*!
Converts a regiser displacement load/store into a register-indexed
load/store for large stack frames, when the stack frame exceeds the
range of a s10 displacement.
*/
int convertDFormToXForm(int dFormOpcode) const;
//! Acquire an unused register in an emergency.
unsigned findScratchRegister(MachineBasicBlock::iterator II,
RegScavenger *RS,
const TargetRegisterClass *RC,
int SPAdj) const;
};
} // end namespace llvm
#endif
|