1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
//===- MRegisterInfo.cpp - Target Register Information Implementation -----===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the MRegisterInfo interface.
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/ADT/BitVector.h"
using namespace llvm;
MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
regclass_iterator RCB, regclass_iterator RCE,
int CFSO, int CFDO)
: Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
assert(NumRegs < FirstVirtualRegister &&
"Target has too many physical registers!");
CallFrameSetupOpcode = CFSO;
CallFrameDestroyOpcode = CFDO;
}
MRegisterInfo::~MRegisterInfo() {}
/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
/// register.
const TargetRegisterClass *
MRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT,
unsigned reg) const {
assert(isPhysicalRegister(reg) && "reg must be a physical register");
// Pick the register class of the right type that contains this physreg.
for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I)
if ((*I)->hasType(VT) && (*I)->contains(reg))
return *I;
assert(false && "Couldn't find the register class");
return 0;
}
/// getAllocatableSetForRC - Toggle the bits that represent allocatable
/// registers for the specific register class.
static void getAllocatableSetForRC(MachineFunction &MF,
const TargetRegisterClass *RC, BitVector &R){
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
E = RC->allocation_order_end(MF); I != E; ++I)
R.set(*I);
}
BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
const TargetRegisterClass *RC) const {
BitVector Allocatable(NumRegs);
if (RC) {
getAllocatableSetForRC(MF, RC, Allocatable);
return Allocatable;
}
for (MRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I)
getAllocatableSetForRC(MF, *I, Allocatable);
return Allocatable;
}
/// getFrameIndexOffset - Returns the displacement from the frame register to
/// the stack frame of the specified index. This is the default implementation
/// which is likely incorrect for the target.
int MRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
MachineFrameInfo *MFI = MF.getFrameInfo();
return MFI->getObjectOffset(FI) + MFI->getStackSize() -
TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
}
/// getInitialFrameState - Returns a list of machine moves that are assumed
/// on entry to a function.
void
MRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
// Default is to do nothing.
}
|
