1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
|
//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Format #2 instruction classes in the SparcV8
//===----------------------------------------------------------------------===//
class F2 : InstV8 { // Format 2 instructions
bits<3> op2;
bits<22> imm22;
let op = 0; // op = 0
let Inst{24-22} = op2;
let Inst{21-0} = imm22;
}
// Specific F2 classes: SparcV8 manual, page 44
//
class F2_1<bits<3> op2Val, dag ops, string asmstr> : F2 {
bits<5> rd;
dag OperandList = ops;
let AsmString = asmstr;
let op2 = op2Val;
let Inst{29-25} = rd;
}
class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr> : F2 {
bits<4> cond;
bit annul = 0; // currently unused
dag OperandList = ops;
let AsmString = asmstr;
let cond = condVal;
let op2 = op2Val;
let Inst{29} = annul;
let Inst{28-25} = cond;
}
//===----------------------------------------------------------------------===//
// Format #3 instruction classes in the SparcV8
//===----------------------------------------------------------------------===//
class F3 : InstV8 {
bits<5> rd;
bits<6> op3;
bits<5> rs1;
let op{1} = 1; // Op = 2 or 3
let Inst{29-25} = rd;
let Inst{24-19} = op3;
let Inst{18-14} = rs1;
}
// Specific F3 classes: SparcV8 manual, page 44
//
class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
string asmstr, list<dag> pattern> : F3 {
bits<8> asi = 0; // asi not currently used in SparcV8
bits<5> rs2;
dag OperandList = ops;
let AsmString = asmstr;
let Pattern = pattern;
let op = opVal;
let op3 = op3val;
let Inst{13} = 0; // i field = 0
let Inst{12-5} = asi; // address space identifier
let Inst{4-0} = rs2;
}
class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
string asmstr, list<dag> pattern> : F3 {
bits<13> simm13;
dag OperandList = ops;
let AsmString = asmstr;
let Pattern = pattern;
let op = opVal;
let op3 = op3val;
let Inst{13} = 1; // i field = 1
let Inst{12-0} = simm13;
}
// floating-point
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
string asmstr> : F3 {
bits<5> rs2;
dag OperandList = ops;
let AsmString = asmstr;
let op = opVal;
let op3 = op3val;
let Inst{13-5} = opfval; // fp opcode
let Inst{4-0} = rs2;
}
|
