blob: 5f829034902f4c3eda10bc76c4907462a94c52fd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
//===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// SystemZ supported processors and features
//===----------------------------------------------------------------------===//
include "SystemZProcessors.td"
//===----------------------------------------------------------------------===//
// Register file description
//===----------------------------------------------------------------------===//
include "SystemZRegisterInfo.td"
//===----------------------------------------------------------------------===//
// Calling convention description
//===----------------------------------------------------------------------===//
include "SystemZCallingConv.td"
//===----------------------------------------------------------------------===//
// Instruction descriptions
//===----------------------------------------------------------------------===//
include "SystemZOperators.td"
include "SystemZOperands.td"
include "SystemZPatterns.td"
include "SystemZInstrFormats.td"
include "SystemZInstrInfo.td"
include "SystemZInstrFP.td"
def SystemZInstrInfo : InstrInfo {}
//===----------------------------------------------------------------------===//
// Assembly parser
//===----------------------------------------------------------------------===//
def SystemZAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
}
//===----------------------------------------------------------------------===//
// Top-level target declaration
//===----------------------------------------------------------------------===//
def SystemZ : Target {
let InstructionSet = SystemZInstrInfo;
let AssemblyParsers = [SystemZAsmParser];
}
|
