1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
|
//===-- XCoreInstrFormats.td - XCore Instruction Formats ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
field bits<32> Inst;
let Namespace = "XCore";
dag OutOperandList = outs;
dag InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;
let Size = sz;
field bits<32> SoftFail = 0;
}
// XCore pseudo instructions format
class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<0, outs, ins, asmstr, pattern> {
let isPseudo = 1;
}
//===----------------------------------------------------------------------===//
// Instruction formats
//===----------------------------------------------------------------------===//
class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{15-11} = opc;
let DecoderMethod = "Decode3RInstruction";
}
class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-27} = opc{8-4};
let Inst{26-20} = 0b1111110;
let Inst{19-16} = opc{3-0};
let Inst{15-11} = 0b11111;
let DecoderMethod = "DecodeL3RInstruction";
}
// L3R with first operand as both a source and a destination.
class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeL3RSrcDstInstruction";
}
class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{15-11} = opc;
let DecoderMethod = "Decode2RUSInstruction";
}
// 2RUS with bitp operand
class _F2RUSBitp<bits<5> opc, dag outs, dag ins, string asmstr,
list<dag> pattern>
: _F2RUS<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "Decode2RUSBitpInstruction";
}
class _FL2RUS<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-27} = opc{8-4};
let Inst{26-20} = 0b1111110;
let Inst{19-16} = opc{3-0};
let Inst{15-11} = 0b11111;
let DecoderMethod = "DecodeL2RUSInstruction";
}
// L2RUS with bitp operand
class _FL2RUSBitp<bits<9> opc, dag outs, dag ins, string asmstr,
list<dag> pattern>
: _FL2RUS<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeL2RUSBitpInstruction";
}
class _FRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
bits<4> a;
bits<6> b;
let Inst{15-10} = opc;
let Inst{9-6} = a;
let Inst{5-0} = b;
}
class _FLRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
bits<4> a;
bits<16> b;
let Inst{31-26} = opc;
let Inst{25-22} = a;
let Inst{21-16} = b{5-0};
let Inst{15-10} = 0b111100;
let Inst{9-0} = b{15-6};
}
class _FU6<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
}
class _FLU6<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
}
class _FU10<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
}
class _FLU10<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
}
class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{15-11} = opc{5-1};
let Inst{4} = opc{0};
let DecoderMethod = "Decode2RInstruction";
}
// 2R with first operand as both a source and a destination.
class _F2RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
list<dag> pattern> : _F2R<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "Decode2RSrcDstInstruction";
}
// Same as 2R with last two operands swapped
class _FR2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: _F2R<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeR2RInstruction";
}
class _FRUS<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{15-11} = opc{5-1};
let Inst{4} = opc{0};
let DecoderMethod = "DecodeRUSInstruction";
}
// RUS with bitp operand
class _FRUSBitp<bits<6> opc, dag outs, dag ins, string asmstr,
list<dag> pattern>
: _FRUS<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeRUSBitpInstruction";
}
// RUS with first operand as both a source and a destination and a bitp second
// operand
class _FRUSSrcDstBitp<bits<6> opc, dag outs, dag ins, string asmstr,
list<dag> pattern>
: _FRUS<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeRUSSrcDstBitpInstruction";
}
class _FL2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-27} = opc{9-5};
let Inst{26-20} = 0b1111110;
let Inst{19-16} = opc{4-1};
let Inst{15-11} = 0b11111;
let Inst{4} = opc{0};
let DecoderMethod = "DecodeL2RInstruction";
}
// Same as L2R with last two operands swapped
class _FLR2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: _FL2R<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeLR2RInstruction";
}
class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
bits<4> a;
let Inst{15-11} = opc{5-1};
let Inst{10-5} = 0b111111;
let Inst{4} = opc{0};
let Inst{3-0} = a;
}
class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{15-11} = opc{9-5};
let Inst{10-5} = 0b111111;
let Inst{4-0} = opc{4-0};
}
class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
}
class _L5R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
}
class _L6R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
}
|
