1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
|
; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
; Verify that for the architectures that are known to have poor latency
; double precision shift instructions we generate alternative sequence
; of instructions with lower latencies instead of shrd instruction.
;uint64_t rshift1(uint64_t a, uint64_t b)
;{
; return (a >> 1) | (b << 63);
;}
; CHECK: rshift1:
; CHECK: shrq {{.*}}
; CHECK-NEXT: shlq $63, {{.*}}
; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
define i64 @rshift1(i64 %a, i64 %b) nounwind readnone uwtable {
%1 = lshr i64 %a, 1
%2 = shl i64 %b, 63
%3 = or i64 %2, %1
ret i64 %3
}
;uint64_t rshift2(uint64_t a, uint64_t b)
;{
; return (a >> 2) | (b << 62);
;}
; CHECK: rshift2:
; CHECK: shrq $2, {{.*}}
; CHECK-NEXT: shlq $62, {{.*}}
; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
define i64 @rshift2(i64 %a, i64 %b) nounwind readnone uwtable {
%1 = lshr i64 %a, 2
%2 = shl i64 %b, 62
%3 = or i64 %2, %1
ret i64 %3
}
;uint64_t rshift7(uint64_t a, uint64_t b)
;{
; return (a >> 7) | (b << 57);
;}
; CHECK: rshift7:
; CHECK: shrq $7, {{.*}}
; CHECK-NEXT: shlq $57, {{.*}}
; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
define i64 @rshift7(i64 %a, i64 %b) nounwind readnone uwtable {
%1 = lshr i64 %a, 7
%2 = shl i64 %b, 57
%3 = or i64 %2, %1
ret i64 %3
}
;uint64_t rshift63(uint64_t a, uint64_t b)
;{
; return (a >> 63) | (b << 1);
;}
; CHECK: rshift63:
; CHECK: shrq $63, {{.*}}
; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
; CHECK-NEXT: orq {{.*}}, {{.*}}
define i64 @rshift63(i64 %a, i64 %b) nounwind readnone uwtable {
%1 = lshr i64 %a, 63
%2 = shl i64 %b, 1
%3 = or i64 %2, %1
ret i64 %3
}
|
