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// This tests to make sure we can parse tree patterns.
// RUN: llvm-tblgen %s
// XFAIL: vg_leak
class TreeNode;
class RegisterClass;
def set : TreeNode;
def plus : TreeNode;
def imm : TreeNode;
def R32 : RegisterClass;
class Inst<dag T> {
dag Pattern = T;
}
def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
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