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authorJob Noorman <jobnoorman@gmail.com>2014-04-02 13:13:56 +0000
committerJob Noorman <jobnoorman@gmail.com>2014-04-02 13:13:56 +0000
commit4e7ec2b053e8659f3ac97702833000b818a41de5 (patch)
treebdb96f74a99c47a17f11e115386601083a9a0d63
parent5d853bf42d854ba45615dfda928088ec5edf06c7 (diff)
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Mark FPB as a reserved register when needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205421 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/MSP430/MSP430RegisterInfo.cpp4
-rw-r--r--test/CodeGen/MSP430/fp.ll12
2 files changed, 15 insertions, 1 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp
index 578443167c..f64017ef25 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.cpp
+++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp
@@ -88,8 +88,10 @@ BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(MSP430::CGW);
// Mark frame pointer as reserved if needed.
- if (TFI->hasFP(MF))
+ if (TFI->hasFP(MF)) {
+ Reserved.set(MSP430::FPB);
Reserved.set(MSP430::FPW);
+ }
return Reserved;
}
diff --git a/test/CodeGen/MSP430/fp.ll b/test/CodeGen/MSP430/fp.ll
index 018090566f..b6ba22e47c 100644
--- a/test/CodeGen/MSP430/fp.ll
+++ b/test/CodeGen/MSP430/fp.ll
@@ -15,3 +15,15 @@ entry:
; CHECK: pop.w r4
ret void
}
+
+; Due to FPB not being marked as reserved, the register allocator used to select
+; r4 as the register for the "r" constraint below. This test verifies that this
+; does not happen anymore. Note that the only reason an ISR is used here is that
+; the register allocator selects r4 first instead of fifth in a normal function.
+define msp430_intrcc void @fpb_alloced() #0 {
+; CHECK_LABEL: fpb_alloced:
+; CHECK-NOT: mov.b #0, r4
+; CHECK: nop
+ call void asm sideeffect "nop", "r"(i8 0)
+ ret void
+}