diff options
| -rw-r--r-- | lib/Target/MSP430/MSP430RegisterInfo.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/MSP430/fp.ll | 12 |
2 files changed, 15 insertions, 1 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp index 578443167c..f64017ef25 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -88,8 +88,10 @@ BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(MSP430::CGW); // Mark frame pointer as reserved if needed. - if (TFI->hasFP(MF)) + if (TFI->hasFP(MF)) { + Reserved.set(MSP430::FPB); Reserved.set(MSP430::FPW); + } return Reserved; } diff --git a/test/CodeGen/MSP430/fp.ll b/test/CodeGen/MSP430/fp.ll index 018090566f..b6ba22e47c 100644 --- a/test/CodeGen/MSP430/fp.ll +++ b/test/CodeGen/MSP430/fp.ll @@ -15,3 +15,15 @@ entry: ; CHECK: pop.w r4 ret void } + +; Due to FPB not being marked as reserved, the register allocator used to select +; r4 as the register for the "r" constraint below. This test verifies that this +; does not happen anymore. Note that the only reason an ISR is used here is that +; the register allocator selects r4 first instead of fifth in a normal function. +define msp430_intrcc void @fpb_alloced() #0 { +; CHECK_LABEL: fpb_alloced: +; CHECK-NOT: mov.b #0, r4 +; CHECK: nop + call void asm sideeffect "nop", "r"(i8 0) + ret void +} |