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//===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/Support/MathExtras.h"
using namespace llvm;
namespace {
class MipsAsmParser : public MCTargetAsmParser {
#define GET_ASSEMBLER_HEADER
#include "MipsGenAsmMatcher.inc"
bool MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out);
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
bool ParseDirective(AsmToken DirectiveID);
OperandMatchResultTy parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
public:
MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
: MCTargetAsmParser() {
}
};
}
namespace {
/// MipsOperand - Instances of this class represent a parsed Mips machine
/// instruction.
class MipsOperand : public MCParsedAsmOperand {
enum KindTy {
k_CondCode,
k_CoprocNum,
k_Immediate,
k_Memory,
k_PostIndexRegister,
k_Register,
k_Token
} Kind;
MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
public:
void addRegOperands(MCInst &Inst, unsigned N) const {
llvm_unreachable("unimplemented!");
}
void addExpr(MCInst &Inst, const MCExpr *Expr) const{
llvm_unreachable("unimplemented!");
}
void addImmOperands(MCInst &Inst, unsigned N) const {
llvm_unreachable("unimplemented!");
}
void addMemOperands(MCInst &Inst, unsigned N) const {
llvm_unreachable("unimplemented!");
}
bool isReg() const { return Kind == k_Register; }
bool isImm() const { return Kind == k_Immediate; }
bool isToken() const { return Kind == k_Token; }
bool isMem() const { return Kind == k_Memory; }
StringRef getToken() const {
assert(Kind == k_Token && "Invalid access!");
return "";
}
unsigned getReg() const {
assert((Kind == k_Register) && "Invalid access!");
return 0;
}
virtual void print(raw_ostream &OS) const {
llvm_unreachable("unimplemented!");
}
};
}
bool MipsAsmParser::
MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
return true;
}
bool MipsAsmParser::
ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
return true;
}
bool MipsAsmParser::
ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return true;
}
bool MipsAsmParser::
ParseDirective(AsmToken DirectiveID) {
return true;
}
MipsAsmParser::OperandMatchResultTy MipsAsmParser::
parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&) {
return MatchOperand_ParseFail;
}
extern "C" void LLVMInitializeMipsAsmParser() {
RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
}
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