diff options
| author | RichardBarry <RichardBarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2009-02-07 17:52:41 +0000 |
|---|---|---|
| committer | RichardBarry <RichardBarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2009-02-07 17:52:41 +0000 |
| commit | b32de1ac44e038d57f465aa27dc37c2c3b5b222d (patch) | |
| tree | 03c5af759f9d14b5b89043cc9190e752ede98f74 | |
| parent | 8ab046e16f1a7fddf49ba3b6132f01ea2b374550 (diff) | |
| download | freertos-b32de1ac44e038d57f465aa27dc37c2c3b5b222d.tar.gz freertos-b32de1ac44e038d57f465aa27dc37c2c3b5b222d.tar.bz2 freertos-b32de1ac44e038d57f465aa27dc37c2c3b5b222d.tar.xz | |
Add MCF52259 demo.
git-svn-id: https://freertos.svn.sourceforge.net/svnroot/freertos/trunk@692 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
60 files changed, 10188 insertions, 0 deletions
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/FreeRTOSConfig.h b/Demo/ColdFire_MCF52259_CodeWarrior/FreeRTOSConfig.h new file mode 100644 index 00000000..d7527e1f --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/FreeRTOSConfig.h @@ -0,0 +1,143 @@ +/*
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.
+
+ This file is part of the FreeRTOS.org distribution.
+
+ FreeRTOS.org is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ FreeRTOS.org is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with FreeRTOS.org; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ A special exception to the GPL can be applied should you wish to distribute
+ a combined work that includes FreeRTOS.org, without being obliged to provide
+ the source code for any proprietary components. See the licensing section
+ of http://www.FreeRTOS.org for full details of how and when the exception
+ can be applied.
+
+ ***************************************************************************
+ ***************************************************************************
+ * *
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
+ * and even write all or part of your application on your behalf. *
+ * See http://www.OpenRTOS.com for details of the services we provide to *
+ * expedite your project. *
+ * *
+ ***************************************************************************
+ ***************************************************************************
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/* Library includes. */
+#include "common.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 80000000 )
+#define configTICK_RATE_HZ ( ( portTickType ) 100 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 160 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 30 * 1024 ) )
+#define configMAX_TASK_NAME_LEN ( 12 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 0
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 0
+#define configUSE_COUNTING_SEMAPHORES 0
+
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+
+#define configYIELD_INTERRUPT_VECTOR 16UL
+#define configKERNEL_INTERRUPT_PRIORITY 1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
+
+void vApplicationSetupInterrupts( void );
+
+/* Ethernet configuration. */
+#define configMAC_0 0x00
+#define configMAC_1 0x04
+#define configMAC_2 0x9F
+#define configMAC_3 0x00
+#define configMAC_4 0xAB
+#define configMAC_5 0x2B
+
+#define configIP_ADDR0 192
+#define configIP_ADDR1 168
+#define configIP_ADDR2 0
+#define configIP_ADDR3 11
+
+#define configGW_ADDR0 172
+#define configGW_ADDR1 25
+#define configGW_ADDR2 218
+#define configGW_ADDR3 3
+
+#define configNET_MASK0 255
+#define configNET_MASK1 255
+#define configNET_MASK2 255
+#define configNET_MASK3 0
+
+#define configNUM_FEC_TX_BUFFERS 2
+#define configNUM_FEC_RX_BUFFERS 4
+#define configFEC_BUFFER_SIZE 1520
+#define configUSE_PROMISCUOUS_MODE 0
+#define configETHERNET_INPUT_TASK_STACK_SIZE ( 320 )
+#define configETHERNET_INPUT_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+
+#define configPHY_ADDRESS 1
+
+#if ( configFEC_BUFFER_SIZE & 0x0F ) != 0
+ #error configFEC_BUFFER_SIZE must be a multiple of 16.
+#endif
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/FreeRTOS_Tick_Setup.c b/Demo/ColdFire_MCF52259_CodeWarrior/FreeRTOS_Tick_Setup.c new file mode 100644 index 00000000..188486cd --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/FreeRTOS_Tick_Setup.c @@ -0,0 +1,136 @@ +/*
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.
+
+ This file is part of the FreeRTOS.org distribution.
+
+ FreeRTOS.org is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ FreeRTOS.org is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with FreeRTOS.org; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ A special exception to the GPL can be applied should you wish to distribute
+ a combined work that includes FreeRTOS.org, without being obliged to provide
+ the source code for any proprietary components. See the licensing section
+ of http://www.FreeRTOS.org for full details of how and when the exception
+ can be applied.
+
+ ***************************************************************************
+ ***************************************************************************
+ * *
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
+ * and even write all or part of your application on your behalf. *
+ * See http://www.OpenRTOS.com for details of the services we provide to *
+ * expedite your project. *
+ * *
+ ***************************************************************************
+ ***************************************************************************
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+__declspec(interrupt:0) void vPIT0InterruptHandler( void );
+
+/* Constants used to configure the interrupts. */
+#define portPRESCALE_VALUE 64
+#define portPRESCALE_REG_SETTING ( 5 << 8 )
+#define portPIT_INTERRUPT_ENABLED ( 0x08 )
+#define configPIT0_INTERRUPT_VECTOR ( 55 )
+
+/*
+ * FreeRTOS.org requires two interrupts - a tick interrupt generated from a
+ * timer source, and a spare interrupt vector used for context switching.
+ * The configuration below uses PIT0 for the former, and vector 16 for the
+ * latter. **IF YOUR APPLICATION HAS BOTH OF THESE INTERRUPTS FREE THEN YOU DO
+ * NOT NEED TO CHANGE ANY OF THIS CODE** - otherwise instructions are provided
+ * here for using alternative interrupt sources.
+ *
+ * To change the tick interrupt source:
+ *
+ * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever
+ * peripheral is to be used to generate the tick interrupt. The name of the
+ * handler function (currently vPIT0InterruptHandler()) should also be updated
+ * to indicate which peripheral is generating the interrupt.
+ *
+ * 2) Make sure the interrupt source is cleared within the interrupt handler function.
+ * Currently vPIT0InterruptHandler() clears the PIT0 interrupt.
+ *
+ * 3) Update the vector table within mcf5225x_vectors.s to install the tick
+ * interrupt handler in the correct vector position.
+ *
+ * To change the spare interrupt source:
+ *
+ * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever
+ * interrupt vector is to be used. Make sure you use a spare interrupt on interrupt
+ * controller 0, otherwise the register used to request context switches will also
+ * require modification.
+ *
+ * 2) Change the definition of configYIELD_INTERRUPT_VECTOR within FreeRTOSConfig.h
+ * to be correct for your chosen interrupt vector.
+ *
+ * 3) Update the vector table within mcf5225x_vectors.s to install the handler
+ * _vPortYieldISR() in the correct vector position (by default vector number 16 is
+ * used).
+ */
+void vApplicationSetupInterrupts( void )
+{
+const unsigned portSHORT usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ );
+
+ /* Configure interrupt priority and level and unmask interrupt for PIT0. */
+ MCF_INTC0_ICR55 = ( 1 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 );
+
+ /* Do the same for vector 63 (interrupt controller 0. I don't think the
+ write to MCF_INTC0_IMRH is actually required here but is included for
+ completeness. */
+ MCF_INTC0_ICR16 = ( 0 | configKERNEL_INTERRUPT_PRIORITY << 3 );
+ MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK16 | 0x01 );
+
+ /* Configure PIT0 to generate the RTOS tick. */
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;
+ MCF_PIT0_PCSR = ( portPRESCALE_REG_SETTING | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );
+ MCF_PIT0_PMR = usCompareMatchValue;
+}
+/*-----------------------------------------------------------*/
+
+__declspec(interrupt:0) void vPIT0InterruptHandler( void )
+{
+unsigned portLONG ulSavedInterruptMask;
+
+ /* Clear the PIT0 interrupt. */
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;
+
+ /* Increment the RTOS tick. */
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ vTaskIncrementTick();
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+
+ /* If we are using the pre-emptive scheduler then also request a
+ context switch as incrementing the tick could have unblocked a task. */
+ #if configUSE_PREEMPTION == 1
+ {
+ taskYIELD();
+ }
+ #endif
+}
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259.h new file mode 100644 index 00000000..a68770cf --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259.h @@ -0,0 +1,95 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_H__
+#define __MCF52259_H__
+
+
+/********************************************************************/
+/*
+ * The basic data types
+ */
+
+typedef unsigned char uint8; /* 8 bits */
+typedef unsigned short int uint16; /* 16 bits */
+typedef unsigned long int uint32; /* 32 bits */
+
+typedef signed char int8; /* 8 bits */
+typedef signed short int int16; /* 16 bits */
+typedef signed long int int32; /* 32 bits */
+
+typedef volatile uint8 vuint8; /* 8 bits */
+typedef volatile uint16 vuint16; /* 16 bits */
+typedef volatile uint32 vuint32; /* 32 bits */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#pragma define_section system ".system" far_absolute RW
+
+/***
+ * MCF52259 Derivative Memory map definitions from linker command files:
+ * __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
+ * symbols must be defined in the linker command file.
+ */
+
+extern __declspec(system) uint8 __IPSBAR[];
+extern __declspec(system) uint8 __RAMBAR[];
+extern __declspec(system) uint8 __RAMBAR_SIZE[];
+extern __declspec(system) uint8 __FLASHBAR[];
+extern __declspec(system) uint8 __FLASHBAR_SIZE[];
+
+#define IPSBAR_ADDRESS (uint32)__IPSBAR
+#define RAMBAR_ADDRESS (uint32)__RAMBAR
+#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE
+#define FLASHBAR_ADDRESS (uint32)__FLASHBAR
+#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE
+
+
+#include "MCF52259_SCM.h"
+#include "MCF52259_FBCS.h"
+#include "MCF52259_DMA.h"
+#include "MCF52259_UART.h"
+#include "MCF52259_I2C.h"
+#include "MCF52259_QSPI.h"
+#include "MCF52259_DTIM.h"
+#include "MCF52259_INTC.h"
+#include "MCF52259_FEC.h"
+#include "MCF52259_GPIO.h"
+#include "MCF52259_PAD.h"
+#include "MCF52259_RCM.h"
+#include "MCF52259_CCM.h"
+#include "MCF52259_PMM.h"
+#include "MCF52259_CLOCK.h"
+#include "MCF52259_EPORT.h"
+#include "MCF52259_BWT.h"
+#include "MCF52259_PIT.h"
+#include "MCF52259_FlexCAN.h"
+#include "MCF52259_CANMB.h"
+#include "MCF52259_RTC.h"
+#include "MCF52259_ADC.h"
+#include "MCF52259_GPT.h"
+#include "MCF52259_PWM.h"
+#include "MCF52259_USB_OTG.h"
+#include "MCF52259_CFM.h"
+#include "MCF52259_RNGA.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __MCF52259_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_ADC.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_ADC.h new file mode 100644 index 00000000..f1b35ea7 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_ADC.h @@ -0,0 +1,201 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_ADC_H__
+#define __MCF52259_ADC_H__
+
+
+/*********************************************************************
+*
+* Analog-to-Digital Converter (ADC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_ADC_CTRL1 (*(vuint16*)(0x40190000))
+#define MCF_ADC_CTRL2 (*(vuint16*)(0x40190002))
+#define MCF_ADC_ADZCC (*(vuint16*)(0x40190004))
+#define MCF_ADC_ADLST1 (*(vuint16*)(0x40190006))
+#define MCF_ADC_ADLST2 (*(vuint16*)(0x40190008))
+#define MCF_ADC_ADSDIS (*(vuint16*)(0x4019000A))
+#define MCF_ADC_ADSTAT (*(vuint16*)(0x4019000C))
+#define MCF_ADC_ADLSTAT (*(vuint16*)(0x4019000E))
+#define MCF_ADC_ADZCSTAT (*(vuint16*)(0x40190010))
+#define MCF_ADC_ADRSLT0 (*(vuint16*)(0x40190012))
+#define MCF_ADC_ADRSLT1 (*(vuint16*)(0x40190014))
+#define MCF_ADC_ADRSLT2 (*(vuint16*)(0x40190016))
+#define MCF_ADC_ADRSLT3 (*(vuint16*)(0x40190018))
+#define MCF_ADC_ADRSLT4 (*(vuint16*)(0x4019001A))
+#define MCF_ADC_ADRSLT5 (*(vuint16*)(0x4019001C))
+#define MCF_ADC_ADRSLT6 (*(vuint16*)(0x4019001E))
+#define MCF_ADC_ADRSLT7 (*(vuint16*)(0x40190020))
+#define MCF_ADC_ADLLMT0 (*(vuint16*)(0x40190022))
+#define MCF_ADC_ADLLMT1 (*(vuint16*)(0x40190024))
+#define MCF_ADC_ADLLMT2 (*(vuint16*)(0x40190026))
+#define MCF_ADC_ADLLMT3 (*(vuint16*)(0x40190028))
+#define MCF_ADC_ADLLMT4 (*(vuint16*)(0x4019002A))
+#define MCF_ADC_ADLLMT5 (*(vuint16*)(0x4019002C))
+#define MCF_ADC_ADLLMT6 (*(vuint16*)(0x4019002E))
+#define MCF_ADC_ADLLMT7 (*(vuint16*)(0x40190030))
+#define MCF_ADC_ADHLMT0 (*(vuint16*)(0x40190032))
+#define MCF_ADC_ADHLMT1 (*(vuint16*)(0x40190034))
+#define MCF_ADC_ADHLMT2 (*(vuint16*)(0x40190036))
+#define MCF_ADC_ADHLMT3 (*(vuint16*)(0x40190038))
+#define MCF_ADC_ADHLMT4 (*(vuint16*)(0x4019003A))
+#define MCF_ADC_ADHLMT5 (*(vuint16*)(0x4019003C))
+#define MCF_ADC_ADHLMT6 (*(vuint16*)(0x4019003E))
+#define MCF_ADC_ADHLMT7 (*(vuint16*)(0x40190040))
+#define MCF_ADC_ADOFS0 (*(vuint16*)(0x40190042))
+#define MCF_ADC_ADOFS1 (*(vuint16*)(0x40190044))
+#define MCF_ADC_ADOFS2 (*(vuint16*)(0x40190046))
+#define MCF_ADC_ADOFS3 (*(vuint16*)(0x40190048))
+#define MCF_ADC_ADOFS4 (*(vuint16*)(0x4019004A))
+#define MCF_ADC_ADOFS5 (*(vuint16*)(0x4019004C))
+#define MCF_ADC_ADOFS6 (*(vuint16*)(0x4019004E))
+#define MCF_ADC_ADOFS7 (*(vuint16*)(0x40190050))
+#define MCF_ADC_POWER (*(vuint16*)(0x40190052))
+#define MCF_ADC_CAL (*(vuint16*)(0x40190054))
+#define MCF_ADC_ADRSLT(x) (*(vuint16*)(0x40190012 + ((x)*0x2)))
+#define MCF_ADC_ADLLMT(x) (*(vuint16*)(0x40190022 + ((x)*0x2)))
+#define MCF_ADC_ADHLMT(x) (*(vuint16*)(0x40190032 + ((x)*0x2)))
+#define MCF_ADC_ADOFS(x) (*(vuint16*)(0x40190042 + ((x)*0x2)))
+
+
+/* Bit definitions and macros for MCF_ADC_CTRL1 */
+#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x7)<<0)
+#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0xF)<<0x4)
+#define MCF_ADC_CTRL1_HLMTIE (0x100)
+#define MCF_ADC_CTRL1_LLMTIE (0x200)
+#define MCF_ADC_CTRL1_ZCIE (0x400)
+#define MCF_ADC_CTRL1_EOSIE0 (0x800)
+#define MCF_ADC_CTRL1_SYNC0 (0x1000)
+#define MCF_ADC_CTRL1_START0 (0x2000)
+#define MCF_ADC_CTRL1_STOP0 (0x4000)
+
+/* Bit definitions and macros for MCF_ADC_CTRL2 */
+#define MCF_ADC_CTRL2_DIV(x) (((x)&0x1F)<<0)
+#define MCF_ADC_CTRL2_SIMULT (0x20)
+#define MCF_ADC_CTRL2_EOSIE1 (0x800)
+#define MCF_ADC_CTRL2_SYNC1 (0x1000)
+#define MCF_ADC_CTRL2_START1 (0x2000)
+#define MCF_ADC_CTRL2_STOP1 (0x4000)
+
+/* Bit definitions and macros for MCF_ADC_ADZCC */
+#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x3)<<0)
+#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x3)<<0x2)
+#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x3)<<0x4)
+#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x3)<<0x6)
+#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x3)<<0x8)
+#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x3)<<0xA)
+#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x3)<<0xC)
+#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x3)<<0xE)
+
+/* Bit definitions and macros for MCF_ADC_ADLST1 */
+#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x7)<<0)
+#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x7)<<0x4)
+#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x7)<<0x8)
+#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x7)<<0xC)
+
+/* Bit definitions and macros for MCF_ADC_ADLST2 */
+#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x7)<<0)
+#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x7)<<0x4)
+#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x7)<<0x8)
+#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x7)<<0xC)
+
+/* Bit definitions and macros for MCF_ADC_ADSDIS */
+#define MCF_ADC_ADSDIS_DS0 (0x1)
+#define MCF_ADC_ADSDIS_DS1 (0x2)
+#define MCF_ADC_ADSDIS_DS2 (0x4)
+#define MCF_ADC_ADSDIS_DS3 (0x8)
+#define MCF_ADC_ADSDIS_DS4 (0x10)
+#define MCF_ADC_ADSDIS_DS5 (0x20)
+#define MCF_ADC_ADSDIS_DS6 (0x40)
+#define MCF_ADC_ADSDIS_DS7 (0x80)
+
+/* Bit definitions and macros for MCF_ADC_ADSTAT */
+#define MCF_ADC_ADSTAT_RDY0 (0x1)
+#define MCF_ADC_ADSTAT_RDY1 (0x2)
+#define MCF_ADC_ADSTAT_RDY2 (0x4)
+#define MCF_ADC_ADSTAT_RDY3 (0x8)
+#define MCF_ADC_ADSTAT_RDY4 (0x10)
+#define MCF_ADC_ADSTAT_RDY5 (0x20)
+#define MCF_ADC_ADSTAT_RDY6 (0x40)
+#define MCF_ADC_ADSTAT_RDY7 (0x80)
+#define MCF_ADC_ADSTAT_HLMTI (0x100)
+#define MCF_ADC_ADSTAT_LLMTI (0x200)
+#define MCF_ADC_ADSTAT_ZCI (0x400)
+#define MCF_ADC_ADSTAT_EOSI0 (0x800)
+#define MCF_ADC_ADSTAT_EOSI1 (0x1000)
+#define MCF_ADC_ADSTAT_CIP1 (0x4000)
+#define MCF_ADC_ADSTAT_CIP0 (0x8000)
+
+/* Bit definitions and macros for MCF_ADC_ADLSTAT */
+#define MCF_ADC_ADLSTAT_LLS0 (0x1)
+#define MCF_ADC_ADLSTAT_LLS1 (0x2)
+#define MCF_ADC_ADLSTAT_LLS2 (0x4)
+#define MCF_ADC_ADLSTAT_LLS3 (0x8)
+#define MCF_ADC_ADLSTAT_LLS4 (0x10)
+#define MCF_ADC_ADLSTAT_LLS5 (0x20)
+#define MCF_ADC_ADLSTAT_LLS6 (0x40)
+#define MCF_ADC_ADLSTAT_LLS7 (0x80)
+#define MCF_ADC_ADLSTAT_HLS0 (0x100)
+#define MCF_ADC_ADLSTAT_HLS1 (0x200)
+#define MCF_ADC_ADLSTAT_HLS2 (0x400)
+#define MCF_ADC_ADLSTAT_HLS3 (0x800)
+#define MCF_ADC_ADLSTAT_HLS4 (0x1000)
+#define MCF_ADC_ADLSTAT_HLS5 (0x2000)
+#define MCF_ADC_ADLSTAT_HLS6 (0x4000)
+#define MCF_ADC_ADLSTAT_HLS7 (0x8000)
+
+/* Bit definitions and macros for MCF_ADC_ADZCSTAT */
+#define MCF_ADC_ADZCSTAT_ZCS0 (0x1)
+#define MCF_ADC_ADZCSTAT_ZCS1 (0x2)
+#define MCF_ADC_ADZCSTAT_ZCS2 (0x4)
+#define MCF_ADC_ADZCSTAT_ZCS3 (0x8)
+#define MCF_ADC_ADZCSTAT_ZCS4 (0x10)
+#define MCF_ADC_ADZCSTAT_ZCS5 (0x20)
+#define MCF_ADC_ADZCSTAT_ZCS6 (0x40)
+#define MCF_ADC_ADZCSTAT_ZCS7 (0x80)
+
+/* Bit definitions and macros for MCF_ADC_ADRSLT */
+#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0xFFF)<<0x3)
+#define MCF_ADC_ADRSLT_SEXT (0x8000)
+
+/* Bit definitions and macros for MCF_ADC_ADLLMT */
+#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0xFFF)<<0x3)
+
+/* Bit definitions and macros for MCF_ADC_ADHLMT */
+#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0xFFF)<<0x3)
+
+/* Bit definitions and macros for MCF_ADC_ADOFS */
+#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0xFFF)<<0x3)
+
+/* Bit definitions and macros for MCF_ADC_POWER */
+#define MCF_ADC_POWER_PD0 (0x1)
+#define MCF_ADC_POWER_PD1 (0x2)
+#define MCF_ADC_POWER_PD2 (0x4)
+#define MCF_ADC_POWER_APD (0x8)
+#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x3F)<<0x4)
+#define MCF_ADC_POWER_PSTS0 (0x400)
+#define MCF_ADC_POWER_PSTS1 (0x800)
+#define MCF_ADC_POWER_PSTS2 (0x1000)
+#define MCF_ADC_POWER_ASB (0x8000)
+
+/* Bit definitions and macros for MCF_ADC_CAL */
+#define MCF_ADC_CAL_SEL_VREFL (0x4000)
+#define MCF_ADC_CAL_SEL_VREFH (0x8000)
+
+
+#endif /* __MCF52259_ADC_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_BWT.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_BWT.h new file mode 100644 index 00000000..8e3c696e --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_BWT.h @@ -0,0 +1,50 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_BWT_H__
+#define __MCF52259_BWT_H__
+
+
+/*********************************************************************
+*
+* Backup Watchdog Timer Module (BWT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_BWT_WCR (*(vuint16*)(0x40140000))
+#define MCF_BWT_WMR (*(vuint16*)(0x40140002))
+#define MCF_BWT_WCNTR (*(vuint16*)(0x40140004))
+#define MCF_BWT_WSR (*(vuint16*)(0x40140006))
+
+
+/* Bit definitions and macros for MCF_BWT_WCR */
+#define MCF_BWT_WCR_EN (0x1)
+#define MCF_BWT_WCR_DBG (0x2)
+#define MCF_BWT_WCR_DOZE (0x4)
+#define MCF_BWT_WCR_WAIT (0x8)
+#define MCF_BWT_WCR_STOP (0x10)
+
+/* Bit definitions and macros for MCF_BWT_WMR */
+#define MCF_BWT_WMR_WM(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_BWT_WCNTR */
+#define MCF_BWT_WCNTR_WC(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_BWT_WSR */
+#define MCF_BWT_WSR_WS(x) (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF52259_BWT_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CANMB.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CANMB.h new file mode 100644 index 00000000..f8a6bd0a --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CANMB.h @@ -0,0 +1,202 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_CANMB_H__
+#define __MCF52259_CANMB_H__
+
+
+/*********************************************************************
+*
+* Flex Controller Area Network Module (FlexCAN) message buffers
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CANMB_CODE0 (*(vuint8 *)(&__IPSBAR[0x170080]))
+#define MCF_CANMB_CTRL0 (*(vuint8 *)(&__IPSBAR[0x170081]))
+#define MCF_CANMB_TIME0 (*(vuint16*)(&__IPSBAR[0x170082]))
+#define MCF_CANMB_ID0 (*(vuint32*)(&__IPSBAR[0x170084]))
+#define MCF_CANMB_DATA_WORD_1_0 (*(vuint16*)(&__IPSBAR[0x170088]))
+#define MCF_CANMB_DATA_WORD_2_0 (*(vuint16*)(&__IPSBAR[0x17008A]))
+#define MCF_CANMB_DATA_WORD_3_0 (*(vuint16*)(&__IPSBAR[0x17008C]))
+#define MCF_CANMB_DATA_WORD_4_0 (*(vuint16*)(&__IPSBAR[0x17008E]))
+#define MCF_CANMB_CODE1 (*(vuint8 *)(&__IPSBAR[0x170090]))
+#define MCF_CANMB_CTRL1 (*(vuint8 *)(&__IPSBAR[0x170091]))
+#define MCF_CANMB_TIME1 (*(vuint16*)(&__IPSBAR[0x170092]))
+#define MCF_CANMB_ID1 (*(vuint32*)(&__IPSBAR[0x170094]))
+#define MCF_CANMB_DATA_WORD_1_1 (*(vuint16*)(&__IPSBAR[0x170098]))
+#define MCF_CANMB_DATA_WORD_2_1 (*(vuint16*)(&__IPSBAR[0x17009A]))
+#define MCF_CANMB_DATA_WORD_3_1 (*(vuint16*)(&__IPSBAR[0x17009C]))
+#define MCF_CANMB_DATA_WORD_4_1 (*(vuint16*)(&__IPSBAR[0x17009E]))
+#define MCF_CANMB_CODE2 (*(vuint8 *)(&__IPSBAR[0x1700A0]))
+#define MCF_CANMB_CTRL2 (*(vuint8 *)(&__IPSBAR[0x1700A1]))
+#define MCF_CANMB_TIME2 (*(vuint16*)(&__IPSBAR[0x1700A2]))
+#define MCF_CANMB_ID2 (*(vuint32*)(&__IPSBAR[0x1700A4]))
+#define MCF_CANMB_DATA_WORD_1_2 (*(vuint16*)(&__IPSBAR[0x1700A8]))
+#define MCF_CANMB_DATA_WORD_2_2 (*(vuint16*)(&__IPSBAR[0x1700AA]))
+#define MCF_CANMB_DATA_WORD_3_2 (*(vuint16*)(&__IPSBAR[0x1700AC]))
+#define MCF_CANMB_DATA_WORD_4_2 (*(vuint16*)(&__IPSBAR[0x1700AE]))
+#define MCF_CANMB_CODE3 (*(vuint8 *)(&__IPSBAR[0x1700B0]))
+#define MCF_CANMB_CTRL3 (*(vuint8 *)(&__IPSBAR[0x1700B1]))
+#define MCF_CANMB_TIME3 (*(vuint16*)(&__IPSBAR[0x1700B2]))
+#define MCF_CANMB_ID3 (*(vuint32*)(&__IPSBAR[0x1700B4]))
+#define MCF_CANMB_DATA_WORD_1_3 (*(vuint16*)(&__IPSBAR[0x1700B8]))
+#define MCF_CANMB_DATA_WORD_2_3 (*(vuint16*)(&__IPSBAR[0x1700BA]))
+#define MCF_CANMB_DATA_WORD_3_3 (*(vuint16*)(&__IPSBAR[0x1700BC]))
+#define MCF_CANMB_DATA_WORD_4_3 (*(vuint16*)(&__IPSBAR[0x1700BE]))
+#define MCF_CANMB_CODE4 (*(vuint8 *)(&__IPSBAR[0x1700C0]))
+#define MCF_CANMB_CTRL4 (*(vuint8 *)(&__IPSBAR[0x1700C1]))
+#define MCF_CANMB_TIME4 (*(vuint16*)(&__IPSBAR[0x1700C2]))
+#define MCF_CANMB_ID4 (*(vuint32*)(&__IPSBAR[0x1700C4]))
+#define MCF_CANMB_DATA_WORD_1_4 (*(vuint16*)(&__IPSBAR[0x1700C8]))
+#define MCF_CANMB_DATA_WORD_2_4 (*(vuint16*)(&__IPSBAR[0x1700CA]))
+#define MCF_CANMB_DATA_WORD_3_4 (*(vuint16*)(&__IPSBAR[0x1700CC]))
+#define MCF_CANMB_DATA_WORD_4_4 (*(vuint16*)(&__IPSBAR[0x1700CE]))
+#define MCF_CANMB_CODE5 (*(vuint8 *)(&__IPSBAR[0x1700D0]))
+#define MCF_CANMB_CTRL5 (*(vuint8 *)(&__IPSBAR[0x1700D1]))
+#define MCF_CANMB_TIME5 (*(vuint16*)(&__IPSBAR[0x1700D2]))
+#define MCF_CANMB_ID5 (*(vuint32*)(&__IPSBAR[0x1700D4]))
+#define MCF_CANMB_DATA_WORD_1_5 (*(vuint16*)(&__IPSBAR[0x1700D8]))
+#define MCF_CANMB_DATA_WORD_2_5 (*(vuint16*)(&__IPSBAR[0x1700DA]))
+#define MCF_CANMB_DATA_WORD_3_5 (*(vuint16*)(&__IPSBAR[0x1700DC]))
+#define MCF_CANMB_DATA_WORD_4_5 (*(vuint16*)(&__IPSBAR[0x1700DE]))
+#define MCF_CANMB_CODE6 (*(vuint8 *)(&__IPSBAR[0x1700E0]))
+#define MCF_CANMB_CTRL6 (*(vuint8 *)(&__IPSBAR[0x1700E1]))
+#define MCF_CANMB_TIME6 (*(vuint16*)(&__IPSBAR[0x1700E2]))
+#define MCF_CANMB_ID6 (*(vuint32*)(&__IPSBAR[0x1700E4]))
+#define MCF_CANMB_DATA_WORD_1_6 (*(vuint16*)(&__IPSBAR[0x1700E8]))
+#define MCF_CANMB_DATA_WORD_2_6 (*(vuint16*)(&__IPSBAR[0x1700EA]))
+#define MCF_CANMB_DATA_WORD_3_6 (*(vuint16*)(&__IPSBAR[0x1700EC]))
+#define MCF_CANMB_DATA_WORD_4_6 (*(vuint16*)(&__IPSBAR[0x1700EE]))
+#define MCF_CANMB_CODE7 (*(vuint8 *)(&__IPSBAR[0x1700F0]))
+#define MCF_CANMB_CTRL7 (*(vuint8 *)(&__IPSBAR[0x1700F1]))
+#define MCF_CANMB_TIME7 (*(vuint16*)(&__IPSBAR[0x1700F2]))
+#define MCF_CANMB_ID7 (*(vuint32*)(&__IPSBAR[0x1700F4]))
+#define MCF_CANMB_DATA_WORD_1_7 (*(vuint16*)(&__IPSBAR[0x1700F8]))
+#define MCF_CANMB_DATA_WORD_2_7 (*(vuint16*)(&__IPSBAR[0x1700FA]))
+#define MCF_CANMB_DATA_WORD_3_7 (*(vuint16*)(&__IPSBAR[0x1700FC]))
+#define MCF_CANMB_DATA_WORD_4_7 (*(vuint16*)(&__IPSBAR[0x1700FE]))
+#define MCF_CANMB_CODE8 (*(vuint8 *)(&__IPSBAR[0x170100]))
+#define MCF_CANMB_CTRL8 (*(vuint8 *)(&__IPSBAR[0x170101]))
+#define MCF_CANMB_TIME8 (*(vuint16*)(&__IPSBAR[0x170102]))
+#define MCF_CANMB_ID8 (*(vuint32*)(&__IPSBAR[0x170104]))
+#define MCF_CANMB_DATA_WORD_1_8 (*(vuint16*)(&__IPSBAR[0x170108]))
+#define MCF_CANMB_DATA_WORD_2_8 (*(vuint16*)(&__IPSBAR[0x17010A]))
+#define MCF_CANMB_DATA_WORD_3_8 (*(vuint16*)(&__IPSBAR[0x17010C]))
+#define MCF_CANMB_DATA_WORD_4_8 (*(vuint16*)(&__IPSBAR[0x17010E]))
+#define MCF_CANMB_CODE9 (*(vuint8 *)(&__IPSBAR[0x170110]))
+#define MCF_CANMB_CTRL9 (*(vuint8 *)(&__IPSBAR[0x170111]))
+#define MCF_CANMB_TIME9 (*(vuint16*)(&__IPSBAR[0x170112]))
+#define MCF_CANMB_ID9 (*(vuint32*)(&__IPSBAR[0x170114]))
+#define MCF_CANMB_DATA_WORD_1_9 (*(vuint16*)(&__IPSBAR[0x170118]))
+#define MCF_CANMB_DATA_WORD_2_9 (*(vuint16*)(&__IPSBAR[0x17011A]))
+#define MCF_CANMB_DATA_WORD_3_9 (*(vuint16*)(&__IPSBAR[0x17011C]))
+#define MCF_CANMB_DATA_WORD_4_9 (*(vuint16*)(&__IPSBAR[0x17011E]))
+#define MCF_CANMB_CODE10 (*(vuint8 *)(&__IPSBAR[0x170120]))
+#define MCF_CANMB_CTRL10 (*(vuint8 *)(&__IPSBAR[0x170121]))
+#define MCF_CANMB_TIME10 (*(vuint16*)(&__IPSBAR[0x170122]))
+#define MCF_CANMB_ID10 (*(vuint32*)(&__IPSBAR[0x170124]))
+#define MCF_CANMB_DATA_WORD_1_10 (*(vuint16*)(&__IPSBAR[0x170128]))
+#define MCF_CANMB_DATA_WORD_2_10 (*(vuint16*)(&__IPSBAR[0x17012A]))
+#define MCF_CANMB_DATA_WORD_3_10 (*(vuint16*)(&__IPSBAR[0x17012C]))
+#define MCF_CANMB_DATA_WORD_4_10 (*(vuint16*)(&__IPSBAR[0x17012E]))
+#define MCF_CANMB_CODE11 (*(vuint8 *)(&__IPSBAR[0x170130]))
+#define MCF_CANMB_CTRL11 (*(vuint8 *)(&__IPSBAR[0x170131]))
+#define MCF_CANMB_TIME11 (*(vuint16*)(&__IPSBAR[0x170132]))
+#define MCF_CANMB_ID11 (*(vuint32*)(&__IPSBAR[0x170134]))
+#define MCF_CANMB_DATA_WORD_1_11 (*(vuint16*)(&__IPSBAR[0x170138]))
+#define MCF_CANMB_DATA_WORD_2_11 (*(vuint16*)(&__IPSBAR[0x17013A]))
+#define MCF_CANMB_DATA_WORD_3_11 (*(vuint16*)(&__IPSBAR[0x17013C]))
+#define MCF_CANMB_DATA_WORD_4_11 (*(vuint16*)(&__IPSBAR[0x17013E]))
+#define MCF_CANMB_CODE12 (*(vuint8 *)(&__IPSBAR[0x170140]))
+#define MCF_CANMB_CTRL12 (*(vuint8 *)(&__IPSBAR[0x170141]))
+#define MCF_CANMB_TIME12 (*(vuint16*)(&__IPSBAR[0x170142]))
+#define MCF_CANMB_ID12 (*(vuint32*)(&__IPSBAR[0x170144]))
+#define MCF_CANMB_DATA_WORD_1_ (*(vuint16*)(&__IPSBAR[0x170148]))
+#define MCF_CANMB_DATA_WORD_2_12 (*(vuint16*)(&__IPSBAR[0x17014A]))
+#define MCF_CANMB_DATA_WORD_3_12 (*(vuint16*)(&__IPSBAR[0x17014C]))
+#define MCF_CANMB_DATA_WORD_4_12 (*(vuint16*)(&__IPSBAR[0x17014E]))
+#define MCF_CANMB_CODE13 (*(vuint8 *)(&__IPSBAR[0x170150]))
+#define MCF_CANMB_CTRL13 (*(vuint8 *)(&__IPSBAR[0x170151]))
+#define MCF_CANMB_TIME13 (*(vuint16*)(&__IPSBAR[0x170152]))
+#define MCF_CANMB_ID13 (*(vuint32*)(&__IPSBAR[0x170154]))
+#define MCF_CANMB_DATA_WORD_1_13 (*(vuint16*)(&__IPSBAR[0x170158]))
+#define MCF_CANMB_DATA_WORD_2_13 (*(vuint16*)(&__IPSBAR[0x17015A]))
+#define MCF_CANMB_DATA_WORD_3_13 (*(vuint16*)(&__IPSBAR[0x17015C]))
+#define MCF_CANMB_DATA_WORD_4_13 (*(vuint16*)(&__IPSBAR[0x17015E]))
+#define MCF_CANMB_CODE14 (*(vuint8 *)(&__IPSBAR[0x170160]))
+#define MCF_CANMB_CTRL14 (*(vuint8 *)(&__IPSBAR[0x170161]))
+#define MCF_CANMB_TIME14 (*(vuint16*)(&__IPSBAR[0x170162]))
+#define MCF_CANMB_ID14 (*(vuint32*)(&__IPSBAR[0x170164]))
+#define MCF_CANMB_DATA_WORD_1_14 (*(vuint16*)(&__IPSBAR[0x170168]))
+#define MCF_CANMB_DATA_WORD_2_14 (*(vuint16*)(&__IPSBAR[0x17016A]))
+#define MCF_CANMB_DATA_WORD_3_14 (*(vuint16*)(&__IPSBAR[0x17016C]))
+#define MCF_CANMB_DATA_WORD_4_14 (*(vuint16*)(&__IPSBAR[0x17016E]))
+#define MCF_CANMB_CODE15 (*(vuint8 *)(&__IPSBAR[0x170170]))
+#define MCF_CANMB_CTRL15 (*(vuint8 *)(&__IPSBAR[0x170171]))
+#define MCF_CANMB_TIME15 (*(vuint16*)(&__IPSBAR[0x170172]))
+#define MCF_CANMB_ID15 (*(vuint32*)(&__IPSBAR[0x170174]))
+#define MCF_CANMB_DATA_WORD_1_15 (*(vuint16*)(&__IPSBAR[0x170178]))
+#define MCF_CANMB_DATA_WORD_2_15 (*(vuint16*)(&__IPSBAR[0x17017A]))
+#define MCF_CANMB_DATA_WORD_3_15 (*(vuint16*)(&__IPSBAR[0x17017C]))
+#define MCF_CANMB_DATA_WORD_4_15 (*(vuint16*)(&__IPSBAR[0x17017E]))
+#define MCF_CANMB_CODE(x) (*(vuint8 *)(&__IPSBAR[0x170080 + ((x)*0x10)]))
+#define MCF_CANMB_CTRL(x) (*(vuint8 *)(&__IPSBAR[0x170081 + ((x)*0x10)]))
+#define MCF_CANMB_TIME(x) (*(vuint16*)(&__IPSBAR[0x170082 + ((x)*0x10)]))
+#define MCF_CANMB_ID(x) (*(vuint32*)(&__IPSBAR[0x170084 + ((x)*0x10)]))
+#define MCF_CANMB_DATA_WORD_1(x) (*(vuint16*)(&__IPSBAR[0x170088 + ((x)*0x10)]))
+#define MCF_CANMB_DATA_WORD_2(x) (*(vuint16*)(&__IPSBAR[0x17008A + ((x)*0x10)]))
+#define MCF_CANMB_DATA_WORD_3(x) (*(vuint16*)(&__IPSBAR[0x17008C + ((x)*0x10)]))
+#define MCF_CANMB_DATA_WORD_4(x) (*(vuint16*)(&__IPSBAR[0x17008E + ((x)*0x10)]))
+
+
+/* Other macros */
+#define MCF_CANMB_BYTE(x,y) (*(vuint8 *)(&__IPSBAR[((0x170088 + ((x)*0x10)+y))]))
+
+
+/* Bit definitions and macros for MCF_CANMB_CODE */
+#define MCF_CANMB_CODE_CODE(x) (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_CANMB_CTRL */
+#define MCF_CANMB_CTRL_LENGTH(x) (((x)&0xF)<<0)
+#define MCF_CANMB_CTRL_RTR (0x10)
+#define MCF_CANMB_CTRL_IDE (0x20)
+#define MCF_CANMB_CTRL_SRR (0x40)
+
+/* Bit definitions and macros for MCF_CANMB_TIME */
+#define MCF_CANMB_TIME_TIME_STAMP(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_CANMB_ID */
+#define MCF_CANMB_ID_EXT(x) (((x)&0x3FFFF)<<0)
+#define MCF_CANMB_ID_STD(x) (((x)&0x7FF)<<0x12)
+
+/* Bit definitions and macros for MCF_CANMB_DATA_WORD_1 */
+#define MCF_CANMB_DATA_WORD_1_DATA_BYTE_1(x) (((x)&0xFF)<<0)
+#define MCF_CANMB_DATA_WORD_1_DATA_BYTE_0(x) (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_CANMB_DATA_WORD_2 */
+#define MCF_CANMB_DATA_WORD_2_DATA_BYTE_3(x) (((x)&0xFF)<<0)
+#define MCF_CANMB_DATA_WORD_2_DATA_BYTE_2(x) (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_CANMB_DATA_WORD_3 */
+#define MCF_CANMB_DATA_WORD_3_DATA_BYTE_5(x) (((x)&0xFF)<<0)
+#define MCF_CANMB_DATA_WORD_3_DATA_BYTE_4(x) (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_CANMB_DATA_WORD_4 */
+#define MCF_CANMB_DATA_WORD_4_DATA_BYTE_7(x) (((x)&0xFF)<<0)
+#define MCF_CANMB_DATA_WORD_4_DATA_BYTE_6(x) (((x)&0xFF)<<0x8)
+
+
+#endif /* __MCF52259_CANMB_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CCM.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CCM.h new file mode 100644 index 00000000..1688979e --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CCM.h @@ -0,0 +1,51 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_CCM_H__
+#define __MCF52259_CCM_H__
+
+
+/*********************************************************************
+*
+* Chip Configuration Module (CCM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CCM_CCR (*(vuint16*)(0x40110004))
+#define MCF_CCM_RCON (*(vuint16*)(0x40110008))
+#define MCF_CCM_CIR (*(vuint16*)(0x4011000A))
+#define MCF_CCM_CCE (*(vuint16*)(0x40110010))
+
+
+/* Bit definitions and macros for MCF_CCM_CCR */
+#define MCF_CCM_CCR_Mode(x) (((x)&0x7)<<0x8)
+#define MCF_CCM_CCR_MODE_SINGLECHIP (0x600)
+#define MCF_CCM_CCR_MODE_EZPORT (0x500)
+#define MCF_CCM_CCR_LOAD (0x8000)
+
+/* Bit definitions and macros for MCF_CCM_RCON */
+#define MCF_CCM_RCON_RLOAD (0x20)
+
+/* Bit definitions and macros for MCF_CCM_CIR */
+#define MCF_CCM_CIR_PRN(x) (((x)&0x3F)<<0)
+#define MCF_CCM_CIR_PIN(x) (((x)&0x3FF)<<0x6)
+
+/* Bit definitions and macros for MCF_CCM_CCE */
+#define MCF_CCM_CCE_USBEND (0x4000)
+#define MCF_CCM_CCE_MBMOD (0x8000)
+
+
+#endif /* __MCF52259_CCM_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CFM.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CFM.h new file mode 100644 index 00000000..3d7af990 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CFM.h @@ -0,0 +1,84 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_CFM_H__
+#define __MCF52259_CFM_H__
+
+
+/*********************************************************************
+*
+* ColdFire Flash Module (CFM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CFM_CFMMCR (*(vuint16*)(0x401D0000))
+#define MCF_CFM_CFMCLKD (*(vuint8 *)(0x401D0002))
+#define MCF_CFM_CFMSEC (*(vuint32*)(0x401D0008))
+#define MCF_CFM_CFMPROT (*(vuint32*)(0x401D0010))
+#define MCF_CFM_CFMSACC (*(vuint32*)(0x401D0014))
+#define MCF_CFM_CFMDACC (*(vuint32*)(0x401D0018))
+#define MCF_CFM_CFMUSTAT (*(vuint8 *)(0x401D0020))
+#define MCF_CFM_CFMCMD (*(vuint8 *)(0x401D0024))
+#define MCF_CFM_CFMCLKSEL (*(vuint16*)(0x401D004A))
+
+
+/* Bit definitions and macros for MCF_CFM_CFMMCR */
+#define MCF_CFM_CFMMCR_KEYACC (0x20)
+#define MCF_CFM_CFMMCR_CCIE (0x40)
+#define MCF_CFM_CFMMCR_CBEIE (0x80)
+#define MCF_CFM_CFMMCR_AEIE (0x100)
+#define MCF_CFM_CFMMCR_PVIE (0x200)
+#define MCF_CFM_CFMMCR_LOCK (0x400)
+
+/* Bit definitions and macros for MCF_CFM_CFMCLKD */
+#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)
+#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)
+#define MCF_CFM_CFMCLKD_DIVLD (0x80)
+
+/* Bit definitions and macros for MCF_CFM_CFMSEC */
+#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)
+#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)
+#define MCF_CFM_CFMSEC_KEYEN (0x80000000)
+
+/* Bit definitions and macros for MCF_CFM_CFMPROT */
+#define MCF_CFM_CFMPROT_PROTECT(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_CFM_CFMSACC */
+#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_CFM_CFMDACC */
+#define MCF_CFM_CFMDACC_DACC(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_CFM_CFMUSTAT */
+#define MCF_CFM_CFMUSTAT_BLANK (0x4)
+#define MCF_CFM_CFMUSTAT_ACCERR (0x10)
+#define MCF_CFM_CFMUSTAT_PVIOL (0x20)
+#define MCF_CFM_CFMUSTAT_CCIF (0x40)
+#define MCF_CFM_CFMUSTAT_CBEIF (0x80)
+
+/* Bit definitions and macros for MCF_CFM_CFMCMD */
+#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)
+#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)
+#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)
+#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)
+#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)
+#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)
+
+/* Bit definitions and macros for MCF_CFM_CFMCLKSEL */
+#define MCF_CFM_CFMCLKSEL_CLKSEL(x) (((x)&0x3)<<0)
+
+
+#endif /* __MCF52259_CFM_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CLOCK.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CLOCK.h new file mode 100644 index 00000000..3624e7b2 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_CLOCK.h @@ -0,0 +1,95 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_CLOCK_H__
+#define __MCF52259_CLOCK_H__
+
+
+/*********************************************************************
+*
+* Clock Module (CLOCK)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CLOCK_SYNCR (*(vuint16*)(0x40120000))
+#define MCF_CLOCK_SYNSR (*(vuint8 *)(0x40120002))
+#define MCF_CLOCK_ROCR (*(vuint16*)(0x40120004))
+#define MCF_CLOCK_LPDR (*(vuint8 *)(0x40120007))
+#define MCF_CLOCK_CCHR (*(vuint8 *)(0x40120008))
+#define MCF_CLOCK_CCLR (*(vuint8 *)(0x40120009))
+#define MCF_CLOCK_OCHR (*(vuint8 *)(0x4012000A))
+#define MCF_CLOCK_OCLR (*(vuint8 *)(0x4012000B))
+#define MCF_CLOCK_RTCCR (*(vuint8 *)(0x40120012))
+#define MCF_CLOCK_BWCR (*(vuint8 *)(0x40120013))
+
+
+/* Bit definitions and macros for MCF_CLOCK_SYNCR */
+#define MCF_CLOCK_SYNCR_PLLEN (0x1)
+#define MCF_CLOCK_SYNCR_PLLMODE (0x2)
+#define MCF_CLOCK_SYNCR_CLKSRC (0x4)
+#define MCF_CLOCK_SYNCR_FWKUP (0x20)
+#define MCF_CLOCK_SYNCR_DISCLK (0x40)
+#define MCF_CLOCK_SYNCR_LOCEN (0x80)
+#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)
+#define MCF_CLOCK_SYNCR_LOCRE (0x800)
+#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)
+#define MCF_CLOCK_SYNCR_LOLRE (0x8000)
+
+/* Bit definitions and macros for MCF_CLOCK_SYNSR */
+#define MCF_CLOCK_SYNSR_LOCS (0x4)
+#define MCF_CLOCK_SYNSR_LOCK (0x8)
+#define MCF_CLOCK_SYNSR_LOCKS (0x10)
+#define MCF_CLOCK_SYNSR_CRYOSC (0x20)
+#define MCF_CLOCK_SYNSR_OCOSC (0x40)
+#define MCF_CLOCK_SYNSR_EXTOSC (0x80)
+
+/* Bit definitions and macros for MCF_CLOCK_ROCR */
+#define MCF_CLOCK_ROCR_TRIM(x) (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_CLOCK_LPDR */
+#define MCF_CLOCK_LPDR_LPD(x) (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_CLOCK_CCHR */
+#define MCF_CLOCK_CCHR_CCHR(x) (((x)&0x7)<<0)
+
+/* Bit definitions and macros for MCF_CLOCK_CCLR */
+#define MCF_CLOCK_CCLR_OSCSEL0 (0x1)
+#define MCF_CLOCK_CCLR_OSCSEL1 (0x2)
+
+/* Bit definitions and macros for MCF_CLOCK_OCHR */
+#define MCF_CLOCK_OCHR_STBY (0x40)
+#define MCF_CLOCK_OCHR_OCOEN (0x80)
+
+/* Bit definitions and macros for MCF_CLOCK_OCLR */
+#define MCF_CLOCK_OCLR_RANGE (0x10)
+#define MCF_CLOCK_OCLR_LPEN (0x20)
+#define MCF_CLOCK_OCLR_REFS (0x40)
+#define MCF_CLOCK_OCLR_OSCEN (0x80)
+
+/* Bit definitions and macros for MCF_CLOCK_RTCCR */
+#define MCF_CLOCK_RTCCR_RTCSEL (0x1)
+#define MCF_CLOCK_RTCCR_LPEN (0x2)
+#define MCF_CLOCK_RTCCR_REFS (0x4)
+#define MCF_CLOCK_RTCCR_KHZEN (0x8)
+#define MCF_CLOCK_RTCCR_OSCEN (0x10)
+#define MCF_CLOCK_RTCCR_EXTALEN (0x40)
+
+/* Bit definitions and macros for MCF_CLOCK_BWCR */
+#define MCF_CLOCK_BWCR_BWDSEL (0x1)
+#define MCF_CLOCK_BWCR_BWDSTOP (0x2)
+
+
+#endif /* __MCF52259_CLOCK_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_DMA.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_DMA.h new file mode 100644 index 00000000..d247ffce --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_DMA.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_DMA_H__
+#define __MCF52259_DMA_H__
+
+
+/*********************************************************************
+*
+* DMA Controller (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA0_SAR (*(vuint32*)(0x40000100))
+#define MCF_DMA0_DAR (*(vuint32*)(0x40000104))
+#define MCF_DMA0_DSR (*(vuint8 *)(0x40000108))
+#define MCF_DMA0_BCR (*(vuint32*)(0x40000108))
+#define MCF_DMA0_DCR (*(vuint32*)(0x4000010C))
+
+#define MCF_DMA1_SAR (*(vuint32*)(0x40000110))
+#define MCF_DMA1_DAR (*(vuint32*)(0x40000114))
+#define MCF_DMA1_DSR (*(vuint8 *)(0x40000118))
+#define MCF_DMA1_BCR (*(vuint32*)(0x40000118))
+#define MCF_DMA1_DCR (*(vuint32*)(0x4000011C))
+
+#define MCF_DMA2_SAR (*(vuint32*)(0x40000120))
+#define MCF_DMA2_DAR (*(vuint32*)(0x40000124))
+#define MCF_DMA2_DSR (*(vuint8 *)(0x40000128))
+#define MCF_DMA2_BCR (*(vuint32*)(0x40000128))
+#define MCF_DMA2_DCR (*(vuint32*)(0x4000012C))
+
+#define MCF_DMA3_SAR (*(vuint32*)(0x40000130))
+#define MCF_DMA3_DAR (*(vuint32*)(0x40000134))
+#define MCF_DMA3_DSR (*(vuint8 *)(0x40000138))
+#define MCF_DMA3_BCR (*(vuint32*)(0x40000138))
+#define MCF_DMA3_DCR (*(vuint32*)(0x4000013C))
+
+#define MCF_DMA_SAR(x) (*(vuint32*)(0x40000100 + ((x)*0x10)))
+#define MCF_DMA_DAR(x) (*(vuint32*)(0x40000104 + ((x)*0x10)))
+#define MCF_DMA_DSR(x) (*(vuint8 *)(0x40000108 + ((x)*0x10)))
+#define MCF_DMA_BCR(x) (*(vuint32*)(0x40000108 + ((x)*0x10)))
+#define MCF_DMA_DCR(x) (*(vuint32*)(0x4000010C + ((x)*0x10)))
+
+
+/* Bit definitions and macros for MCF_DMA_SAR */
+#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DAR */
+#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DSR */
+#define MCF_DMA_DSR_DONE (0x1)
+#define MCF_DMA_DSR_BSY (0x2)
+#define MCF_DMA_DSR_REQ (0x4)
+#define MCF_DMA_DSR_BED (0x10)
+#define MCF_DMA_DSR_BES (0x20)
+#define MCF_DMA_DSR_CE (0x40)
+
+/* Bit definitions and macros for MCF_DMA_BCR */
+#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFF)<<0)
+#define MCF_DMA_BCR_DSR(x) (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_DMA_DCR */
+#define MCF_DMA_DCR_LCH2(x) (((x)&0x3)<<0)
+#define MCF_DMA_DCR_LCH2_CH0 (0)
+#define MCF_DMA_DCR_LCH2_CH1 (0x1)
+#define MCF_DMA_DCR_LCH2_CH2 (0x2)
+#define MCF_DMA_DCR_LCH2_CH3 (0x3)
+#define MCF_DMA_DCR_LCH1(x) (((x)&0x3)<<0x2)
+#define MCF_DMA_DCR_LCH1_CH0 (0)
+#define MCF_DMA_DCR_LCH1_CH1 (0x1)
+#define MCF_DMA_DCR_LCH1_CH2 (0x2)
+#define MCF_DMA_DCR_LCH1_CH3 (0x3)
+#define MCF_DMA_DCR_LINKCC(x) (((x)&0x3)<<0x4)
+#define MCF_DMA_DCR_D_REQ (0x80)
+#define MCF_DMA_DCR_DMOD(x) (((x)&0xF)<<0x8)
+#define MCF_DMA_DCR_DMOD_DIS (0)
+#define MCF_DMA_DCR_DMOD_16 (0x1)
+#define MCF_DMA_DCR_DMOD_32 (0x2)
+#define MCF_DMA_DCR_DMOD_64 (0x3)
+#define MCF_DMA_DCR_DMOD_128 (0x4)
+#define MCF_DMA_DCR_DMOD_256 (0x5)
+#define MCF_DMA_DCR_DMOD_512 (0x6)
+#define MCF_DMA_DCR_DMOD_1K (0x7)
+#define MCF_DMA_DCR_DMOD_2K (0x8)
+#define MCF_DMA_DCR_DMOD_4K (0x9)
+#define MCF_DMA_DCR_DMOD_8K (0xA)
+#define MCF_DMA_DCR_DMOD_16K (0xB)
+#define MCF_DMA_DCR_DMOD_32K (0xC)
+#define MCF_DMA_DCR_DMOD_64K (0xD)
+#define MCF_DMA_DCR_DMOD_128K (0xE)
+#define MCF_DMA_DCR_DMOD_256K (0xF)
+#define MCF_DMA_DCR_SMOD(x) (((x)&0xF)<<0xC)
+#define MCF_DMA_DCR_SMOD_DIS (0)
+#define MCF_DMA_DCR_SMOD_16 (0x1)
+#define MCF_DMA_DCR_SMOD_32 (0x2)
+#define MCF_DMA_DCR_SMOD_64 (0x3)
+#define MCF_DMA_DCR_SMOD_128 (0x4)
+#define MCF_DMA_DCR_SMOD_256 (0x5)
+#define MCF_DMA_DCR_SMOD_512 (0x6)
+#define MCF_DMA_DCR_SMOD_1K (0x7)
+#define MCF_DMA_DCR_SMOD_2K (0x8)
+#define MCF_DMA_DCR_SMOD_4K (0x9)
+#define MCF_DMA_DCR_SMOD_8K (0xA)
+#define MCF_DMA_DCR_SMOD_16K (0xB)
+#define MCF_DMA_DCR_SMOD_32K (0xC)
+#define MCF_DMA_DCR_SMOD_64K (0xD)
+#define MCF_DMA_DCR_SMOD_128K (0xE)
+#define MCF_DMA_DCR_SMOD_256K (0xF)
+#define MCF_DMA_DCR_START (0x10000)
+#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)
+#define MCF_DMA_DCR_DSIZE_LONG (0)
+#define MCF_DMA_DCR_DSIZE_BYTE (0x1)
+#define MCF_DMA_DCR_DSIZE_WORD (0x2)
+#define MCF_DMA_DCR_DSIZE_LINE (0x3)
+#define MCF_DMA_DCR_DINC (0x80000)
+#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)
+#define MCF_DMA_DCR_SSIZE_LONG (0)
+#define MCF_DMA_DCR_SSIZE_BYTE (0x1)
+#define MCF_DMA_DCR_SSIZE_WORD (0x2)
+#define MCF_DMA_DCR_SSIZE_LINE (0x3)
+#define MCF_DMA_DCR_SINC (0x400000)
+#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)
+#define MCF_DMA_DCR_BWC_16K (0x1)
+#define MCF_DMA_DCR_BWC_32K (0x2)
+#define MCF_DMA_DCR_BWC_64K (0x3)
+#define MCF_DMA_DCR_BWC_128K (0x4)
+#define MCF_DMA_DCR_BWC_256K (0x5)
+#define MCF_DMA_DCR_BWC_512K (0x6)
+#define MCF_DMA_DCR_BWC_1024K (0x7)
+#define MCF_DMA_DCR_AA (0x10000000)
+#define MCF_DMA_DCR_CS (0x20000000)
+#define MCF_DMA_DCR_EEXT (0x40000000)
+#define MCF_DMA_DCR_INT (0x80000000)
+
+
+#endif /* __MCF52259_DMA_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_DTIM.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_DTIM.h new file mode 100644 index 00000000..ed4e2d48 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_DTIM.h @@ -0,0 +1,99 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_DTIM_H__
+#define __MCF52259_DTIM_H__
+
+
+/*********************************************************************
+*
+* DMA Timers (DTIM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DTIM0_DTMR (*(vuint16*)(0x40000400))
+#define MCF_DTIM0_DTXMR (*(vuint8 *)(0x40000402))
+#define MCF_DTIM0_DTER (*(vuint8 *)(0x40000403))
+#define MCF_DTIM0_DTRR (*(vuint32*)(0x40000404))
+#define MCF_DTIM0_DTCR (*(vuint32*)(0x40000408))
+#define MCF_DTIM0_DTCN (*(vuint32*)(0x4000040C))
+
+#define MCF_DTIM1_DTMR (*(vuint16*)(0x40000440))
+#define MCF_DTIM1_DTXMR (*(vuint8 *)(0x40000442))
+#define MCF_DTIM1_DTER (*(vuint8 *)(0x40000443))
+#define MCF_DTIM1_DTRR (*(vuint32*)(0x40000444))
+#define MCF_DTIM1_DTCR (*(vuint32*)(0x40000448))
+#define MCF_DTIM1_DTCN (*(vuint32*)(0x4000044C))
+
+#define MCF_DTIM2_DTMR (*(vuint16*)(0x40000480))
+#define MCF_DTIM2_DTXMR (*(vuint8 *)(0x40000482))
+#define MCF_DTIM2_DTER (*(vuint8 *)(0x40000483))
+#define MCF_DTIM2_DTRR (*(vuint32*)(0x40000484))
+#define MCF_DTIM2_DTCR (*(vuint32*)(0x40000488))
+#define MCF_DTIM2_DTCN (*(vuint32*)(0x4000048C))
+
+#define MCF_DTIM3_DTMR (*(vuint16*)(0x400004C0))
+#define MCF_DTIM3_DTXMR (*(vuint8 *)(0x400004C2))
+#define MCF_DTIM3_DTER (*(vuint8 *)(0x400004C3))
+#define MCF_DTIM3_DTRR (*(vuint32*)(0x400004C4))
+#define MCF_DTIM3_DTCR (*(vuint32*)(0x400004C8))
+#define MCF_DTIM3_DTCN (*(vuint32*)(0x400004CC))
+
+#define MCF_DTIM_DTMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))
+#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0x40000402 + ((x)*0x40)))
+#define MCF_DTIM_DTER(x) (*(vuint8 *)(0x40000403 + ((x)*0x40)))
+#define MCF_DTIM_DTRR(x) (*(vuint32*)(0x40000404 + ((x)*0x40)))
+#define MCF_DTIM_DTCR(x) (*(vuint32*)(0x40000408 + ((x)*0x40)))
+#define MCF_DTIM_DTCN(x) (*(vuint32*)(0x4000040C + ((x)*0x40)))
+
+
+/* Bit definitions and macros for MCF_DTIM_DTMR */
+#define MCF_DTIM_DTMR_RST (0x1)
+#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)
+#define MCF_DTIM_DTMR_CLK_STOP (0)
+#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)
+#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)
+#define MCF_DTIM_DTMR_CLK_DTIN (0x6)
+#define MCF_DTIM_DTMR_FRR (0x8)
+#define MCF_DTIM_DTMR_ORRI (0x10)
+#define MCF_DTIM_DTMR_OM (0x20)
+#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)
+#define MCF_DTIM_DTMR_CE_NONE (0)
+#define MCF_DTIM_DTMR_CE_RISE (0x40)
+#define MCF_DTIM_DTMR_CE_FALL (0x80)
+#define MCF_DTIM_DTMR_CE_ANY (0xC0)
+#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_DTIM_DTXMR */
+#define MCF_DTIM_DTXMR_MODE16 (0x1)
+#define MCF_DTIM_DTXMR_HALTED (0x40)
+#define MCF_DTIM_DTXMR_DMAEN (0x80)
+
+/* Bit definitions and macros for MCF_DTIM_DTER */
+#define MCF_DTIM_DTER_CAP (0x1)
+#define MCF_DTIM_DTER_REF (0x2)
+
+/* Bit definitions and macros for MCF_DTIM_DTRR */
+#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DTIM_DTCR */
+#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DTIM_DTCN */
+#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF52259_DTIM_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_EPORT.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_EPORT.h new file mode 100644 index 00000000..ec4fc82b --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_EPORT.h @@ -0,0 +1,123 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_EPORT_H__
+#define __MCF52259_EPORT_H__
+
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR (*(vuint16*)(0x40130000))
+#define MCF_EPORT_EPDDR (*(vuint8 *)(0x40130002))
+#define MCF_EPORT_EPIER (*(vuint8 *)(0x40130003))
+#define MCF_EPORT_EPDR (*(vuint8 *)(0x40130004))
+#define MCF_EPORT_EPPDR (*(vuint8 *)(0x40130005))
+#define MCF_EPORT_EPFR (*(vuint8 *)(0x40130006))
+
+
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
+#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
+#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
+#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
+#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
+#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
+#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
+#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
+#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
+#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
+#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
+#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
+#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
+#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
+#define MCF_EPORT_EPPAR_LEVEL (0)
+#define MCF_EPORT_EPPAR_RISING (0x1)
+#define MCF_EPORT_EPPAR_FALLING (0x2)
+#define MCF_EPORT_EPPAR_BOTH (0x3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1 (0x2)
+#define MCF_EPORT_EPDDR_EPDD2 (0x4)
+#define MCF_EPORT_EPDDR_EPDD3 (0x8)
+#define MCF_EPORT_EPDDR_EPDD4 (0x10)
+#define MCF_EPORT_EPDDR_EPDD5 (0x20)
+#define MCF_EPORT_EPDDR_EPDD6 (0x40)
+#define MCF_EPORT_EPDDR_EPDD7 (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1 (0x2)
+#define MCF_EPORT_EPIER_EPIE2 (0x4)
+#define MCF_EPORT_EPIER_EPIE3 (0x8)
+#define MCF_EPORT_EPIER_EPIE4 (0x10)
+#define MCF_EPORT_EPIER_EPIE5 (0x20)
+#define MCF_EPORT_EPIER_EPIE6 (0x40)
+#define MCF_EPORT_EPIER_EPIE7 (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1 (0x2)
+#define MCF_EPORT_EPDR_EPD2 (0x4)
+#define MCF_EPORT_EPDR_EPD3 (0x8)
+#define MCF_EPORT_EPDR_EPD4 (0x10)
+#define MCF_EPORT_EPDR_EPD5 (0x20)
+#define MCF_EPORT_EPDR_EPD6 (0x40)
+#define MCF_EPORT_EPDR_EPD7 (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1 (0x2)
+#define MCF_EPORT_EPPDR_EPPD2 (0x4)
+#define MCF_EPORT_EPPDR_EPPD3 (0x8)
+#define MCF_EPORT_EPPDR_EPPD4 (0x10)
+#define MCF_EPORT_EPPDR_EPPD5 (0x20)
+#define MCF_EPORT_EPPDR_EPPD6 (0x40)
+#define MCF_EPORT_EPPDR_EPPD7 (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1 (0x2)
+#define MCF_EPORT_EPFR_EPF2 (0x4)
+#define MCF_EPORT_EPFR_EPF3 (0x8)
+#define MCF_EPORT_EPFR_EPF4 (0x10)
+#define MCF_EPORT_EPFR_EPF5 (0x20)
+#define MCF_EPORT_EPFR_EPF6 (0x40)
+#define MCF_EPORT_EPFR_EPF7 (0x80)
+
+
+#endif /* __MCF52259_EPORT_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_FBCS.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_FBCS.h new file mode 100644 index 00000000..5ab12c8f --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_FBCS.h @@ -0,0 +1,83 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_FBCS_H__
+#define __MCF52259_FBCS_H__
+
+
+/*********************************************************************
+*
+* Mini-FlexBus Chip Select Module (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR (*(vuint32*)(0x40000080))
+#define MCF_FBCS0_CSMR (*(vuint32*)(0x40000084))
+#define MCF_FBCS0_CSCR (*(vuint32*)(0x40000088))
+
+#define MCF_FBCS1_CSAR (*(vuint32*)(0x4000008C))
+#define MCF_FBCS1_CSMR (*(vuint32*)(0x40000090))
+#define MCF_FBCS1_CSCR (*(vuint32*)(0x40000094))
+
+#define MCF_FBCS_CSAR(x) (*(vuint32*)(0x40000080 + ((x)*0xC)))
+#define MCF_FBCS_CSMR(x) (*(vuint32*)(0x40000084 + ((x)*0xC)))
+#define MCF_FBCS_CSCR(x) (*(vuint32*)(0x40000088 + ((x)*0xC)))
+
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V (0x1)
+#define MCF_FBCS_CSMR_WP (0x100)
+#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
+#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)
+#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)
+#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)
+#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)
+#define MCF_FBCS_CSMR_BAM_16M (0xFF0000)
+#define MCF_FBCS_CSMR_BAM_8M (0x7F0000)
+#define MCF_FBCS_CSMR_BAM_4M (0x3F0000)
+#define MCF_FBCS_CSMR_BAM_2M (0x1F0000)
+#define MCF_FBCS_CSMR_BAM_1M (0xF0000)
+#define MCF_FBCS_CSMR_BAM_1024K (0xF0000)
+#define MCF_FBCS_CSMR_BAM_512K (0x70000)
+#define MCF_FBCS_CSMR_BAM_256K (0x30000)
+#define MCF_FBCS_CSMR_BAM_128K (0x10000)
+#define MCF_FBCS_CSMR_BAM_64K (0)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW (0x8)
+#define MCF_FBCS_CSCR_BSTR (0x10)
+#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)
+#define MCF_FBCS_CSCR_PS_8 (0x40)
+#define MCF_FBCS_CSCR_PS_16 (0x80)
+#define MCF_FBCS_CSCR_AA (0x100)
+#define MCF_FBCS_CSCR_MUX (0x200)
+#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)
+#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)
+#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)
+#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)
+#define MCF_FBCS_CSCR_SWSEN (0x800000)
+#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)
+
+
+#endif /* __MCF52259_FBCS_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_FEC.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_FEC.h new file mode 100644 index 00000000..89f83283 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_FEC.h @@ -0,0 +1,393 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_FEC_H__
+#define __MCF52259_FEC_H__
+
+
+/*********************************************************************
+*
+* Fast Ethernet Controller(FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC_EIR (*(vuint32*)(0x40001004))
+#define MCF_FEC_EIMR (*(vuint32*)(0x40001008))
+#define MCF_FEC_RDAR (*(vuint32*)(0x40001010))
+#define MCF_FEC_TDAR (*(vuint32*)(0x40001014))
+#define MCF_FEC_ECR (*(vuint32*)(0x40001024))
+#define MCF_FEC_MMFR (*(vuint32*)(0x40001040))
+#define MCF_FEC_MSCR (*(vuint32*)(0x40001044))
+#define MCF_FEC_MIBC (*(vuint32*)(0x40001064))
+#define MCF_FEC_RCR (*(vuint32*)(0x40001084))
+#define MCF_FEC_TCR (*(vuint32*)(0x400010C4))
+#define MCF_FEC_PALR (*(vuint32*)(0x400010E4))
+#define MCF_FEC_PAUR (*(vuint32*)(0x400010E8))
+#define MCF_FEC_OPD (*(vuint32*)(0x400010EC))
+#define MCF_FEC_IAUR (*(vuint32*)(0x40001118))
+#define MCF_FEC_IALR (*(vuint32*)(0x4000111C))
+#define MCF_FEC_GAUR (*(vuint32*)(0x40001120))
+#define MCF_FEC_GALR (*(vuint32*)(0x40001124))
+#define MCF_FEC_TFWR (*(vuint32*)(0x40001144))
+#define MCF_FEC_FRBR (*(vuint32*)(0x4000114C))
+#define MCF_FEC_FRSR (*(vuint32*)(0x40001150))
+#define MCF_FEC_ERDSR (*(vuint32*)(0x40001180))
+#define MCF_FEC_ETSDR (*(vuint32*)(0x40001184))
+#define MCF_FEC_EMRBR (*(vuint32*)(0x40001188))
+#define MCF_FEC_RMON_T_DROP (*(vuint32*)(0x40001200))
+#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(0x40001204))
+#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(0x40001208))
+#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(0x4000120C))
+#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(0x40001210))
+#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(0x40001214))
+#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(0x40001218))
+#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(0x4000121C))
+#define MCF_FEC_RMON_T_JAB (*(vuint32*)(0x40001220))
+#define MCF_FEC_RMON_T_COL (*(vuint32*)(0x40001224))
+#define MCF_FEC_RMON_T_P64 (*(vuint32*)(0x40001228))
+#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(0x4000122C))
+#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(0x40001230))
+#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(0x40001234))
+#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(0x40001238))
+#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(0x4000123C))
+#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(0x40001240))
+#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(0x40001244))
+#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(0x40001248))
+#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(0x4000124C))
+#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(0x40001250))
+#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(0x40001254))
+#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(0x40001258))
+#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(0x4000125C))
+#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(0x40001260))
+#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(0x40001264))
+#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(0x40001268))
+#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(0x4000126C))
+#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(0x40001270))
+#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(0x40001274))
+#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(0x40001284))
+#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(0x40001288))
+#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(0x4000128C))
+#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(0x40001290))
+#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(0x40001294))
+#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(0x40001298))
+#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(0x4000129C))
+#define MCF_FEC_RMON_R_JAB (*(vuint32*)(0x400012A0))
+#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(0x400012A4))
+#define MCF_FEC_RMON_R_P64 (*(vuint32*)(0x400012A8))
+#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(0x400012AC))
+#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(0x400012B0))
+#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(0x400012B4))
+#define MCF_FEC_RMON_R_P512TO1023 (*(vuint32*)(0x400012B8))
+#define MCF_FEC_RMON_R_P1024TO2047 (*(vuint32*)(0x400012BC))
+#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(0x400012C0))
+#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(0x400012C4))
+#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(0x400012C8))
+#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(0x400012CC))
+#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(0x400012D0))
+#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(0x400012D4))
+#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(0x400012D8))
+#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(0x400012DC))
+#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(0x400012E0))
+
+
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_UN (0x80000)
+#define MCF_FEC_EIR_RL (0x100000)
+#define MCF_FEC_EIR_LC (0x200000)
+#define MCF_FEC_EIR_EBERR (0x400000)
+#define MCF_FEC_EIR_MII (0x800000)
+#define MCF_FEC_EIR_RXB (0x1000000)
+#define MCF_FEC_EIR_RXF (0x2000000)
+#define MCF_FEC_EIR_TXB (0x4000000)
+#define MCF_FEC_EIR_TXF (0x8000000)
+#define MCF_FEC_EIR_GRA (0x10000000)
+#define MCF_FEC_EIR_BABT (0x20000000)
+#define MCF_FEC_EIR_BABR (0x40000000)
+#define MCF_FEC_EIR_HBERR (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_UN (0x80000)
+#define MCF_FEC_EIMR_RL (0x100000)
+#define MCF_FEC_EIMR_LC (0x200000)
+#define MCF_FEC_EIMR_EBERR (0x400000)
+#define MCF_FEC_EIMR_MII (0x800000)
+#define MCF_FEC_EIMR_RXB (0x1000000)
+#define MCF_FEC_EIMR_RXF (0x2000000)
+#define MCF_FEC_EIMR_TXB (0x4000000)
+#define MCF_FEC_EIMR_TXF (0x8000000)
+#define MCF_FEC_EIMR_GRA (0x10000000)
+#define MCF_FEC_EIMR_BABT (0x20000000)
+#define MCF_FEC_EIMR_BABR (0x40000000)
+#define MCF_FEC_EIMR_HBERR (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL (0)
+#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_RDAR */
+#define MCF_FEC_RDAR_R_DES_ACTIVE (0x1000000)
+
+/* Bit definitions and macros for MCF_FEC_TDAR */
+#define MCF_FEC_TDAR_X_DES_ACTIVE (0x1000000)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET (0x1)
+#define MCF_FEC_ECR_ETHER_EN (0x2)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
+#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
+#define MCF_FEC_MMFR_TA_10 (0x20000)
+#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
+#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
+#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
+#define MCF_FEC_MMFR_OP_READ (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
+#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
+#define MCF_FEC_MMFR_ST_01 (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP (0x1)
+#define MCF_FEC_RCR_DRT (0x2)
+#define MCF_FEC_RCR_MII_MODE (0x4)
+#define MCF_FEC_RCR_PROM (0x8)
+#define MCF_FEC_RCR_BC_REJ (0x10)
+#define MCF_FEC_RCR_FCE (0x20)
+#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS (0x1)
+#define MCF_FEC_TCR_HBC (0x2)
+#define MCF_FEC_TCR_FDEN (0x4)
+#define MCF_FEC_TCR_TFC_PAUSE (0x8)
+#define MCF_FEC_TCR_RFC_PAUSE (0x10)
+
+/* Bit definitions and macros for MCF_FEC_PALR */
+#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_PAUR */
+#define MCF_FEC_PAUR_TYPE(x) (((x)&0xFFFF)<<0)
+#define MCF_FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_IAUR */
+#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IALR */
+#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GAUR */
+#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GALR */
+#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_TFWR */
+#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x3)<<0)
+#define MCF_FEC_TFWR_X_WMRK_64 (0)
+#define MCF_FEC_TFWR_X_WMRK_128 (0x2)
+#define MCF_FEC_TFWR_X_WMRK_192 (0x3)
+
+/* Bit definitions and macros for MCF_FEC_FRBR */
+#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<0x2)
+
+/* Bit definitions and macros for MCF_FEC_FRSR */
+#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<0x2)
+
+/* Bit definitions and macros for MCF_FEC_ERDSR */
+#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)
+
+/* Bit definitions and macros for MCF_FEC_ETSDR */
+#define MCF_FEC_ETSDR_X_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)
+
+/* Bit definitions and macros for MCF_FEC_EMRBR */
+#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<0x4)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
+#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
+#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
+#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
+#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
+#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
+#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
+#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
+#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
+#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
+#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
+#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
+#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
+#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
+#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
+#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
+#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
+#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
+#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
+#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
+#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
+#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
+#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
+#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
+#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
+#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
+#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
+#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
+#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
+#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
+#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
+#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
+#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
+#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
+#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
+#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
+#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
+#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
+#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
+#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
+#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF52259_FEC_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_FlexCAN.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_FlexCAN.h new file mode 100644 index 00000000..2c55e4c7 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_FlexCAN.h @@ -0,0 +1,140 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_FlexCAN_H__
+#define __MCF52259_FlexCAN_H__
+
+
+/*********************************************************************
+*
+* Flex Controller Area Network (FlexCAN)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FlexCAN_CANMCR (*(vuint32*)(0x40170000))
+#define MCF_FlexCAN_CANCTRL (*(vuint32*)(0x40170004))
+#define MCF_FlexCAN_TIMER (*(vuint32*)(0x40170008))
+#define MCF_FlexCAN_RXGMASK (*(vuint32*)(0x40170010))
+#define MCF_FlexCAN_RX14MASK (*(vuint32*)(0x40170014))
+#define MCF_FlexCAN_RX15MASK (*(vuint32*)(0x40170018))
+#define MCF_FlexCAN_ERRCNT (*(vuint32*)(0x4017001C))
+#define MCF_FlexCAN_ERRSTAT (*(vuint32*)(0x40170020))
+#define MCF_FlexCAN_IMASK (*(vuint32*)(0x40170028))
+#define MCF_FlexCAN_IFLAG (*(vuint32*)(0x40170030))
+
+
+
+/* Bit definitions and macros for MCF_FlexCAN_CANMCR */
+#define MCF_FlexCAN_CANMCR_MAXMB(x) (((x)&0xF)<<0)
+#define MCF_FlexCAN_CANMCR_LPMACK (0x100000)
+#define MCF_FlexCAN_CANMCR_SUPV (0x800000)
+#define MCF_FlexCAN_CANMCR_FRZACK (0x1000000)
+#define MCF_FlexCAN_CANMCR_SOFTRST (0x2000000)
+#define MCF_FlexCAN_CANMCR_NOTRDY (0x8000000)
+#define MCF_FlexCAN_CANMCR_HALT (0x10000000)
+#define MCF_FlexCAN_CANMCR_FRZ (0x40000000)
+#define MCF_FlexCAN_CANMCR_MDIS (0x80000000)
+
+/* Bit definitions and macros for MCF_FlexCAN_CANCTRL */
+#define MCF_FlexCAN_CANCTRL_PROPSEG(x) (((x)&0x7)<<0)
+#define MCF_FlexCAN_CANCTRL_LOM (0x8)
+#define MCF_FlexCAN_CANCTRL_LBUF (0x10)
+#define MCF_FlexCAN_CANCTRL_TSYNC (0x20)
+#define MCF_FlexCAN_CANCTRL_BOFFREC (0x40)
+#define MCF_FlexCAN_CANCTRL_SAMP (0x80)
+#define MCF_FlexCAN_CANCTRL_LPB (0x1000)
+#define MCF_FlexCAN_CANCTRL_CLK_SRC (0x2000)
+#define MCF_FlexCAN_CANCTRL_ERRMSK (0x4000)
+#define MCF_FlexCAN_CANCTRL_BOFFMSK (0x8000)
+#define MCF_FlexCAN_CANCTRL_PSEG2(x) (((x)&0x7)<<0x10)
+#define MCF_FlexCAN_CANCTRL_PSEG1(x) (((x)&0x7)<<0x13)
+#define MCF_FlexCAN_CANCTRL_RJW(x) (((x)&0x3)<<0x16)
+#define MCF_FlexCAN_CANCTRL_PRESDIV(x) (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_FlexCAN_TIMER */
+#define MCF_FlexCAN_TIMER_TIMER(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FlexCAN_RXGMASK */
+#define MCF_FlexCAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FlexCAN_RX14MASK */
+#define MCF_FlexCAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FlexCAN_RX15MASK */
+#define MCF_FlexCAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FlexCAN_ERRCNT */
+#define MCF_FlexCAN_ERRCNT_TXECTR(x) (((x)&0xFF)<<0)
+#define MCF_FlexCAN_ERRCNT_RXECTR(x) (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_FlexCAN_ERRSTAT */
+#define MCF_FlexCAN_ERRSTAT_ERRINT (0x2)
+#define MCF_FlexCAN_ERRSTAT_BOFFINT (0x4)
+#define MCF_FlexCAN_ERRSTAT_FLTCONF(x) (((x)&0x3)<<0x4)
+#define MCF_FlexCAN_ERRSTAT_FLTCONF_ACTIVE (0)
+#define MCF_FlexCAN_ERRSTAT_FLTCONF_PASSIVE (0x10)
+#define MCF_FlexCAN_ERRSTAT_FLTCONF_BUSOFF (0x20)
+#define MCF_FlexCAN_ERRSTAT_TXRX (0x40)
+#define MCF_FlexCAN_ERRSTAT_IDLE (0x80)
+#define MCF_FlexCAN_ERRSTAT_RXWRN (0x100)
+#define MCF_FlexCAN_ERRSTAT_TXWRN (0x200)
+#define MCF_FlexCAN_ERRSTAT_STFERR (0x400)
+#define MCF_FlexCAN_ERRSTAT_FRMERR (0x800)
+#define MCF_FlexCAN_ERRSTAT_CRCERR (0x1000)
+#define MCF_FlexCAN_ERRSTAT_ACKERR (0x2000)
+#define MCF_FlexCAN_ERRSTAT_BIT0ERR (0x4000)
+#define MCF_FlexCAN_ERRSTAT_BIT1ERR (0x8000)
+
+/* Bit definitions and macros for MCF_FlexCAN_IMASK */
+#define MCF_FlexCAN_IMASK_BUF0M (0x1)
+#define MCF_FlexCAN_IMASK_BUF1M (0x2)
+#define MCF_FlexCAN_IMASK_BUF2M (0x4)
+#define MCF_FlexCAN_IMASK_BUF3M (0x8)
+#define MCF_FlexCAN_IMASK_BUF4M (0x10)
+#define MCF_FlexCAN_IMASK_BUF5M (0x20)
+#define MCF_FlexCAN_IMASK_BUF6M (0x40)
+#define MCF_FlexCAN_IMASK_BUF7M (0x80)
+#define MCF_FlexCAN_IMASK_BUF8M (0x100)
+#define MCF_FlexCAN_IMASK_BUF9M (0x200)
+#define MCF_FlexCAN_IMASK_BUF10M (0x400)
+#define MCF_FlexCAN_IMASK_BUF11M (0x800)
+#define MCF_FlexCAN_IMASK_BUF12M (0x1000)
+#define MCF_FlexCAN_IMASK_BUF13M (0x2000)
+#define MCF_FlexCAN_IMASK_BUF14M (0x4000)
+#define MCF_FlexCAN_IMASK_BUF15M (0x8000)
+#define MCF_FlexCAN_IMASK_BUF(x) (0x1<<(x))
+
+/* Bit definitions and macros for MCF_FlexCAN_IFLAG */
+#define MCF_FlexCAN_IFLAG_BUF0I (0x1)
+#define MCF_FlexCAN_IFLAG_BUF1I (0x2)
+#define MCF_FlexCAN_IFLAG_BUF2I (0x4)
+#define MCF_FlexCAN_IFLAG_BUF3I (0x8)
+#define MCF_FlexCAN_IFLAG_BUF4I (0x10)
+#define MCF_FlexCAN_IFLAG_BUF5I (0x20)
+#define MCF_FlexCAN_IFLAG_BUF6I (0x40)
+#define MCF_FlexCAN_IFLAG_BUF7I (0x80)
+#define MCF_FlexCAN_IFLAG_BUF8I (0x100)
+#define MCF_FlexCAN_IFLAG_BUF9I (0x200)
+#define MCF_FlexCAN_IFLAG_BUF10I (0x400)
+#define MCF_FlexCAN_IFLAG_BUF11I (0x800)
+#define MCF_FlexCAN_IFLAG_BUF12I (0x1000)
+#define MCF_FlexCAN_IFLAG_BUF13I (0x2000)
+#define MCF_FlexCAN_IFLAG_BUF14I (0x4000)
+#define MCF_FlexCAN_IFLAG_BUF15I (0x8000)
+#define MCF_FlexCAN_IFLAG_BUF(x) (0x1<<(x))
+
+
+#endif /* __MCF52259_FlexCAN_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_GPIO.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_GPIO.h new file mode 100644 index 00000000..d9617aa7 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_GPIO.h @@ -0,0 +1,1035 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_GPIO_H__
+#define __MCF52259_GPIO_H__
+
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PORTTE (*(vuint8 *)(0x40100000))
+#define MCF_GPIO_DDRTE (*(vuint8 *)(0x40100018))
+#define MCF_GPIO_SETTE (*(vuint8 *)(0x40100030))
+#define MCF_GPIO_CLRTE (*(vuint8 *)(0x40100048))
+#define MCF_GPIO_PTEPAR (*(vuint8 *)(0x40100060))
+
+#define MCF_GPIO_PORTTF (*(vuint8 *)(0x40100001))
+#define MCF_GPIO_DDRTF (*(vuint8 *)(0x40100019))
+#define MCF_GPIO_SETTF (*(vuint8 *)(0x40100031))
+#define MCF_GPIO_CLRTF (*(vuint8 *)(0x40100049))
+#define MCF_GPIO_PTFPAR (*(vuint8 *)(0x40100061))
+
+#define MCF_GPIO_PORTTG (*(vuint8 *)(0x40100002))
+#define MCF_GPIO_DDRTG (*(vuint8 *)(0x4010001A))
+#define MCF_GPIO_SETTG (*(vuint8 *)(0x40100032))
+#define MCF_GPIO_CLRTG (*(vuint8 *)(0x4010004A))
+#define MCF_GPIO_PTGPAR (*(vuint8 *)(0x40100062))
+
+#define MCF_GPIO_PORTTH (*(vuint8 *)(0x40100003))
+#define MCF_GPIO_DDRTH (*(vuint8 *)(0x4010001B))
+#define MCF_GPIO_SETTH (*(vuint8 *)(0x40100033))
+#define MCF_GPIO_CLRTH (*(vuint8 *)(0x4010004B))
+#define MCF_GPIO_PTHPAR (*(vuint16*)(0x40100090))
+
+#define MCF_GPIO_PORTTI (*(vuint8 *)(0x40100004))
+#define MCF_GPIO_DDRTI (*(vuint8 *)(0x4010001C))
+#define MCF_GPIO_SETTI (*(vuint8 *)(0x40100034))
+#define MCF_GPIO_CLRTI (*(vuint8 *)(0x4010004C))
+#define MCF_GPIO_PTIPAR (*(vuint8 *)(0x40100064))
+
+#define MCF_GPIO_PORTTJ (*(vuint8 *)(0x40100006))
+#define MCF_GPIO_DDRTJ (*(vuint8 *)(0x4010001E))
+#define MCF_GPIO_SETTJ (*(vuint8 *)(0x40100036))
+#define MCF_GPIO_CLRTJ (*(vuint8 *)(0x4010004E))
+#define MCF_GPIO_PTJPAR (*(vuint8 *)(0x40100066))
+
+#define MCF_GPIO_PORTNQ (*(vuint8 *)(0x40100008))
+#define MCF_GPIO_DDRNQ (*(vuint8 *)(0x40100020))
+#define MCF_GPIO_SETNQ (*(vuint8 *)(0x40100038))
+#define MCF_GPIO_CLRNQ (*(vuint8 *)(0x40100050))
+#define MCF_GPIO_PNQPAR (*(vuint16*)(0x40100068))
+
+#define MCF_GPIO_PORTAN (*(vuint8 *)(0x4010000A))
+#define MCF_GPIO_DDRAN (*(vuint8 *)(0x40100022))
+#define MCF_GPIO_SETAN (*(vuint8 *)(0x4010003A))
+#define MCF_GPIO_CLRAN (*(vuint8 *)(0x40100052))
+#define MCF_GPIO_PANPAR (*(vuint8 *)(0x4010006A))
+
+#define MCF_GPIO_PORTAS (*(vuint8 *)(0x4010000B))
+#define MCF_GPIO_DDRAS (*(vuint8 *)(0x40100023))
+#define MCF_GPIO_SETAS (*(vuint8 *)(0x4010003B))
+#define MCF_GPIO_CLRAS (*(vuint8 *)(0x40100053))
+#define MCF_GPIO_PASPAR (*(vuint8 *)(0x4010006B))
+
+#define MCF_GPIO_PORTQS (*(vuint8 *)(0x4010000C))
+#define MCF_GPIO_DDRQS (*(vuint8 *)(0x40100024))
+#define MCF_GPIO_SETQS (*(vuint8 *)(0x4010003C))
+#define MCF_GPIO_CLRQS (*(vuint8 *)(0x40100054))
+#define MCF_GPIO_PQSPAR (*(vuint16*)(0x4010006C))
+
+#define MCF_GPIO_PORTTA (*(vuint8 *)(0x4010000E))
+#define MCF_GPIO_DDRTA (*(vuint8 *)(0x40100026))
+#define MCF_GPIO_SETTA (*(vuint8 *)(0x4010003E))
+#define MCF_GPIO_CLRTA (*(vuint8 *)(0x40100056))
+#define MCF_GPIO_PTAPAR (*(vuint8 *)(0x4010006E))
+
+#define MCF_GPIO_PORTTC (*(vuint8 *)(0x4010000F))
+#define MCF_GPIO_DDRTC (*(vuint8 *)(0x40100027))
+#define MCF_GPIO_SETTC (*(vuint8 *)(0x4010003F))
+#define MCF_GPIO_CLRTC (*(vuint8 *)(0x40100057))
+#define MCF_GPIO_PTCPAR (*(vuint8 *)(0x4010006F))
+
+#define MCF_GPIO_PORTUA (*(vuint8 *)(0x40100011))
+#define MCF_GPIO_DDRUA (*(vuint8 *)(0x40100029))
+#define MCF_GPIO_SETUA (*(vuint8 *)(0x40100041))
+#define MCF_GPIO_CLRUA (*(vuint8 *)(0x40100059))
+#define MCF_GPIO_PUAPAR (*(vuint8 *)(0x40100071))
+
+#define MCF_GPIO_PORTUB (*(vuint8 *)(0x40100012))
+#define MCF_GPIO_DDRUB (*(vuint8 *)(0x4010002A))
+#define MCF_GPIO_SETUB (*(vuint8 *)(0x40100042))
+#define MCF_GPIO_CLRUB (*(vuint8 *)(0x4010005A))
+#define MCF_GPIO_PUBPAR (*(vuint8 *)(0x40100072))
+
+#define MCF_GPIO_PORTUC (*(vuint8 *)(0x40100013))
+#define MCF_GPIO_DDRUC (*(vuint8 *)(0x4010002B))
+#define MCF_GPIO_SETUC (*(vuint8 *)(0x40100043))
+#define MCF_GPIO_CLRUC (*(vuint8 *)(0x4010005B))
+#define MCF_GPIO_PUCPAR (*(vuint8 *)(0x40100073))
+
+#define MCF_GPIO_PORTDD (*(vuint8 *)(0x40100014))
+#define MCF_GPIO_DDRDD (*(vuint8 *)(0x4010002C))
+#define MCF_GPIO_SETDD (*(vuint8 *)(0x40100044))
+#define MCF_GPIO_CLRDD (*(vuint8 *)(0x4010005C))
+#define MCF_GPIO_PDDPAR (*(vuint8 *)(0x40100074))
+
+
+
+/* Bit definitions and macros for MCF_GPIO_PORTTE */
+#define MCF_GPIO_PORTTE_PORTTE0 (0x1)
+#define MCF_GPIO_PORTTE_PORTTE1 (0x2)
+#define MCF_GPIO_PORTTE_PORTTE2 (0x4)
+#define MCF_GPIO_PORTTE_PORTTE3 (0x8)
+#define MCF_GPIO_PORTTE_PORTTE4 (0x10)
+#define MCF_GPIO_PORTTE_PORTTE5 (0x20)
+#define MCF_GPIO_PORTTE_PORTTE6 (0x40)
+#define MCF_GPIO_PORTTE_PORTTE7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_DDRTE */
+#define MCF_GPIO_DDRTE_DDRTE0 (0x1)
+#define MCF_GPIO_DDRTE_DDRTE1 (0x2)
+#define MCF_GPIO_DDRTE_DDRTE2 (0x4)
+#define MCF_GPIO_DDRTE_DDRTE3 (0x8)
+#define MCF_GPIO_DDRTE_DDRTE4 (0x10)
+#define MCF_GPIO_DDRTE_DDRTE5 (0x20)
+#define MCF_GPIO_DDRTE_DDRTE6 (0x40)
+#define MCF_GPIO_DDRTE_DDRTE7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_SETTE */
+#define MCF_GPIO_SETTE_SETTE0 (0x1)
+#define MCF_GPIO_SETTE_SETTE1 (0x2)
+#define MCF_GPIO_SETTE_SETTE2 (0x4)
+#define MCF_GPIO_SETTE_SETTE3 (0x8)
+#define MCF_GPIO_SETTE_SETTE4 (0x10)
+#define MCF_GPIO_SETTE_SETTE5 (0x20)
+#define MCF_GPIO_SETTE_SETTE6 (0x40)
+#define MCF_GPIO_SETTE_SETTE7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_CLRTE */
+#define MCF_GPIO_CLRTE_CLRTE0 (0x1)
+#define MCF_GPIO_CLRTE_CLRTE1 (0x2)
+#define MCF_GPIO_CLRTE_CLRTE2 (0x4)
+#define MCF_GPIO_CLRTE_CLRTE3 (0x8)
+#define MCF_GPIO_CLRTE_CLRTE4 (0x10)
+#define MCF_GPIO_CLRTE_CLRTE5 (0x20)
+#define MCF_GPIO_CLRTE_CLRTE6 (0x40)
+#define MCF_GPIO_CLRTE_CLRTE7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PTEPAR */
+#define MCF_GPIO_PTEPAR_PTEPAR0 (0x1)
+#define MCF_GPIO_PTEPAR_MB_A0_GPIO (0)
+#define MCF_GPIO_PTEPAR_MB_A0_MB_A0 (0x1)
+#define MCF_GPIO_PTEPAR_PTEPAR1 (0x2)
+#define MCF_GPIO_PTEPAR_MB_A1_GPIO (0)
+#define MCF_GPIO_PTEPAR_MB_A1_MB_A1 (0x2)
+#define MCF_GPIO_PTEPAR_PTEPAR2 (0x4)
+#define MCF_GPIO_PTEPAR_MB_A2_GPIO (0)
+#define MCF_GPIO_PTEPAR_MB_A2_MB_A2 (0x4)
+#define MCF_GPIO_PTEPAR_PTEPAR3 (0x8)
+#define MCF_GPIO_PTEPAR_MB_A3_GPIO (0)
+#define MCF_GPIO_PTEPAR_MB_A3_MB_A3 (0x8)
+#define MCF_GPIO_PTEPAR_PTEPAR4 (0x10)
+#define MCF_GPIO_PTEPAR_MB_A4_GPIO (0)
+#define MCF_GPIO_PTEPAR_MB_A4_MB_A4 (0x10)
+#define MCF_GPIO_PTEPAR_PTEPAR5 (0x20)
+#define MCF_GPIO_PTEPAR_MB_A5_GPIO (0)
+#define MCF_GPIO_PTEPAR_MB_A5_MB_A5 (0x20)
+#define MCF_GPIO_PTEPAR_PTEPAR6 (0x40)
+#define MCF_GPIO_PTEPAR_MB_A6_GPIO (0)
+#define MCF_GPIO_PTEPAR_MB_A6_MB_A6 (0x40)
+#define MCF_GPIO_PTEPAR_PTEPAR7 (0x80)
+#define MCF_GPIO_PTEPAR_MB_A7_GPIO (0)
+#define MCF_GPIO_PTEPAR_MB_A7_MB_A7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PORTTF */
+#define MCF_GPIO_PORTTF_PORTTF0 (0x1)
+#define MCF_GPIO_PORTTF_PORTTF1 (0x2)
+#define MCF_GPIO_PORTTF_PORTTF2 (0x4)
+#define MCF_GPIO_PORTTF_PORTTF3 (0x8)
+#define MCF_GPIO_PORTTF_PORTTF4 (0x10)
+#define MCF_GPIO_PORTTF_PORTTF5 (0x20)
+#define MCF_GPIO_PORTTF_PORTTF6 (0x40)
+#define MCF_GPIO_PORTTF_PORTTF7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_DDRTF */
+#define MCF_GPIO_DDRTF_DDRTF0 (0x1)
+#define MCF_GPIO_DDRTF_DDRTF1 (0x2)
+#define MCF_GPIO_DDRTF_DDRTF2 (0x4)
+#define MCF_GPIO_DDRTF_DDRTF3 (0x8)
+#define MCF_GPIO_DDRTF_DDRTF4 (0x10)
+#define MCF_GPIO_DDRTF_DDRTF5 (0x20)
+#define MCF_GPIO_DDRTF_DDRTF6 (0x40)
+#define MCF_GPIO_DDRTF_DDRTF7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_SETTF */
+#define MCF_GPIO_SETTF_SETTF0 (0x1)
+#define MCF_GPIO_SETTF_SETTF1 (0x2)
+#define MCF_GPIO_SETTF_SETTF2 (0x4)
+#define MCF_GPIO_SETTF_SETTF3 (0x8)
+#define MCF_GPIO_SETTF_SETTF4 (0x10)
+#define MCF_GPIO_SETTF_SETTF5 (0x20)
+#define MCF_GPIO_SETTF_SETTF6 (0x40)
+#define MCF_GPIO_SETTF_SETTF7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_CLRTF */
+#define MCF_GPIO_CLRTF_CLRTF0 (0x1)
+#define MCF_GPIO_CLRTF_CLRTF1 (0x2)
+#define MCF_GPIO_CLRTF_CLRTF2 (0x4)
+#define MCF_GPIO_CLRTF_CLRTF3 (0x8)
+#define MCF_GPIO_CLRTF_CLRTF4 (0x10)
+#define MCF_GPIO_CLRTF_CLRTF5 (0x20)
+#define MCF_GPIO_CLRTF_CLRTF6 (0x40)
+#define MCF_GPIO_CLRTF_CLRTF7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PTFPAR */
+#define MCF_GPIO_PTFPAR_PTFPAR0 (0x1)
+#define MCF_GPIO_PTFPAR_MB_A8_GPIO (0)
+#define MCF_GPIO_PTFPAR_MB_A8_MB_A8 (0x1)
+#define MCF_GPIO_PTFPAR_PTFPAR1 (0x2)
+#define MCF_GPIO_PTFPAR_MB_A9_GPIO (0)
+#define MCF_GPIO_PTFPAR_MB_A9_MB_A9 (0x2)
+#define MCF_GPIO_PTFPAR_PTFPAR2 (0x4)
+#define MCF_GPIO_PTFPAR_MB_A10_GPIO (0)
+#define MCF_GPIO_PTFPAR_MB_A10_MB_A10 (0x4)
+#define MCF_GPIO_PTFPAR_PTFPAR3 (0x8)
+#define MCF_GPIO_PTFPAR_MB_A11_GPIO (0)
+#define MCF_GPIO_PTFPAR_MB_A11_MB_A11 (0x8)
+#define MCF_GPIO_PTFPAR_PTFPAR4 (0x10)
+#define MCF_GPIO_PTFPAR_MB_A12_GPIO (0)
+#define MCF_GPIO_PTFPAR_MB_A12_MB_A12 (0x10)
+#define MCF_GPIO_PTFPAR_PTFPAR5 (0x20)
+#define MCF_GPIO_PTFPAR_MB_A13_GPIO (0)
+#define MCF_GPIO_PTFPAR_MB_A13_MB_A13 (0x20)
+#define MCF_GPIO_PTFPAR_PTFPAR6 (0x40)
+#define MCF_GPIO_PTFPAR_MB_A14_GPIO (0)
+#define MCF_GPIO_PTFPAR_MB_A14_MB_A14 (0x40)
+#define MCF_GPIO_PTFPAR_PTFPAR7 (0x80)
+#define MCF_GPIO_PTFPAR_MB_A15_GPIO (0)
+#define MCF_GPIO_PTFPAR_MB_A15_MB_A15 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PORTTG */
+#define MCF_GPIO_PORTTG_PORTTG0 (0x1)
+#define MCF_GPIO_PORTTG_PORTTG1 (0x2)
+#define MCF_GPIO_PORTTG_PORTTG2 (0x4)
+#define MCF_GPIO_PORTTG_PORTTG3 (0x8)
+#define MCF_GPIO_PORTTG_PORTTG4 (0x10)
+#define MCF_GPIO_PORTTG_PORTTG5 (0x20)
+#define MCF_GPIO_PORTTG_PORTTG6 (0x40)
+#define MCF_GPIO_PORTTG_PORTTG7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_DDRTG */
+#define MCF_GPIO_DDRTG_DDRTG0 (0x1)
+#define MCF_GPIO_DDRTG_DDRTG1 (0x2)
+#define MCF_GPIO_DDRTG_DDRTG2 (0x4)
+#define MCF_GPIO_DDRTG_DDRTG3 (0x8)
+#define MCF_GPIO_DDRTG_DDRTG4 (0x10)
+#define MCF_GPIO_DDRTG_DDRTG5 (0x20)
+#define MCF_GPIO_DDRTG_DDRTG6 (0x40)
+#define MCF_GPIO_DDRTG_DDRTG7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_SETTG */
+#define MCF_GPIO_SETTG_SETTG0 (0x1)
+#define MCF_GPIO_SETTG_SETTG1 (0x2)
+#define MCF_GPIO_SETTG_SETTG2 (0x4)
+#define MCF_GPIO_SETTG_SETTG3 (0x8)
+#define MCF_GPIO_SETTG_SETTG4 (0x10)
+#define MCF_GPIO_SETTG_SETTG5 (0x20)
+#define MCF_GPIO_SETTG_SETTG6 (0x40)
+#define MCF_GPIO_SETTG_SETTG7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_CLRTG */
+#define MCF_GPIO_CLRTG_CLRTG0 (0x1)
+#define MCF_GPIO_CLRTG_CLRTG1 (0x2)
+#define MCF_GPIO_CLRTG_CLRTG2 (0x4)
+#define MCF_GPIO_CLRTG_CLRTG3 (0x8)
+#define MCF_GPIO_CLRTG_CLRTG4 (0x10)
+#define MCF_GPIO_CLRTG_CLRTG5 (0x20)
+#define MCF_GPIO_CLRTG_CLRTG6 (0x40)
+#define MCF_GPIO_CLRTG_CLRTG7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PTGPAR */
+#define MCF_GPIO_PTGPAR_PTGPAR0 (0x1)
+#define MCF_GPIO_PTGPAR_MB_A16_GPIO (0)
+#define MCF_GPIO_PTGPAR_MB_A16_MB_A16 (0x1)
+#define MCF_GPIO_PTGPAR_PTGPAR1 (0x2)
+#define MCF_GPIO_PTGPAR_MB_A17_GPIO (0)
+#define MCF_GPIO_PTGPAR_MB_A17_MB_A17 (0x2)
+#define MCF_GPIO_PTGPAR_PTGPAR2 (0x4)
+#define MCF_GPIO_PTGPAR_MB_A18_GPIO (0)
+#define MCF_GPIO_PTGPAR_MB_A18_MB_A18 (0x4)
+#define MCF_GPIO_PTGPAR_PTGPAR3 (0x8)
+#define MCF_GPIO_PTGPAR_MB_A19_GPIO (0)
+#define MCF_GPIO_PTGPAR_MB_A19_MB_A19 (0x8)
+#define MCF_GPIO_PTGPAR_PTGPAR4 (0x10)
+#define MCF_GPIO_PTGPAR_PTGPAR5 (0x20)
+#define MCF_GPIO_PTGPAR_MB_CS1_GPIO (0)
+#define MCF_GPIO_PTGPAR_MB_CS0_MB_CS0 (0x20)
+#define MCF_GPIO_PTGPAR_PTGPAR6 (0x40)
+#define MCF_GPIO_PTGPAR_MB_OE_GPIO (0)
+#define MCF_GPIO_PTGPAR_MB_OE_MB_OE (0x40)
+#define MCF_GPIO_PTGPAR_PTGPAR7 (0x80)
+#define MCF_GPIO_PTGPAR_MB_RW_GPIO (0)
+#define MCF_GPIO_PTGPAR_MB_RW_MB_RW (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PORTTH */
+#define MCF_GPIO_PORTTH_PORTTH0 (0x1)
+#define MCF_GPIO_PORTTH_PORTTH1 (0x2)
+#define MCF_GPIO_PORTTH_PORTTH2 (0x4)
+#define MCF_GPIO_PORTTH_PORTTH3 (0x8)
+#define MCF_GPIO_PORTTH_PORTTH4 (0x10)
+#define MCF_GPIO_PORTTH_PORTTH5 (0x20)
+#define MCF_GPIO_PORTTH_PORTTH6 (0x40)
+#define MCF_GPIO_PORTTH_PORTTH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_DDRTH */
+#define MCF_GPIO_DDRTH_DDRTH0 (0x1)
+#define MCF_GPIO_DDRTH_DDRTH1 (0x2)
+#define MCF_GPIO_DDRTH_DDRTH2 (0x4)
+#define MCF_GPIO_DDRTH_DDRTH3 (0x8)
+#define MCF_GPIO_DDRTH_DDRTH4 (0x10)
+#define MCF_GPIO_DDRTH_DDRTH5 (0x20)
+#define MCF_GPIO_DDRTH_DDRTH6 (0x40)
+#define MCF_GPIO_DDRTH_DDRTH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_SETTH */
+#define MCF_GPIO_SETTH_SETTH0 (0x1)
+#define MCF_GPIO_SETTH_SETTH1 (0x2)
+#define MCF_GPIO_SETTH_SETTH2 (0x4)
+#define MCF_GPIO_SETTH_SETTH3 (0x8)
+#define MCF_GPIO_SETTH_SETTH4 (0x10)
+#define MCF_GPIO_SETTH_SETTH5 (0x20)
+#define MCF_GPIO_SETTH_SETTH6 (0x40)
+#define MCF_GPIO_SETTH_SETTH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_CLRTH */
+#define MCF_GPIO_CLRTH_CLRTH0 (0x1)
+#define MCF_GPIO_CLRTH_CLRTH1 (0x2)
+#define MCF_GPIO_CLRTH_CLRTH2 (0x4)
+#define MCF_GPIO_CLRTH_CLRTH3 (0x8)
+#define MCF_GPIO_CLRTH_CLRTH4 (0x10)
+#define MCF_GPIO_CLRTH_CLRTH5 (0x20)
+#define MCF_GPIO_CLRTH_CLRTH6 (0x40)
+#define MCF_GPIO_CLRTH_CLRTH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PTHPAR */
+#define MCF_GPIO_PTHPAR_PTHPAR0(x) (((x)&0x3)<<0)
+#define MCF_GPIO_PTHPAR_MB_D0_GPIO (0)
+#define MCF_GPIO_PTHPAR_MB_D0_MB_D0 (0x1)
+#define MCF_GPIO_PTHPAR_MB_D0_SYNCB (0x2)
+#define MCF_GPIO_PTHPAR_PTHPAR1(x) (((x)&0x3)<<0x2)
+#define MCF_GPIO_PTHPAR_MB_D1_GPIO (0)
+#define MCF_GPIO_PTHPAR_MB_D1_MB_D1 (0x4)
+#define MCF_GPIO_PTHPAR_MB_D1_SYNCA (0x8)
+#define MCF_GPIO_PTHPAR_PTHPAR2(x) (((x)&0x3)<<0x4)
+#define MCF_GPIO_PTHPAR_MB_D2_GPIO (0)
+#define MCF_GPIO_PTHPAR_MB_D2_MB_D2 (0x10)
+#define MCF_GPIO_PTHPAR_MB_D2_USB_VBUSE (0x20)
+#define MCF_GPIO_PTHPAR_PTHPAR3(x) (((x)&0x3)<<0x6)
+#define MCF_GPIO_PTHPAR_MB_D3_GPIO (0)
+#define MCF_GPIO_PTHPAR_MB_D3_MB_D3 (0x40)
+#define MCF_GPIO_PTHPAR_MB_D3_USB_VBUSD (0x80)
+#define MCF_GPIO_PTHPAR_PTHPAR4(x) (((x)&0x3)<<0x8)
+#define MCF_GPIO_PTHPAR_MB_D4_GPIO (0)
+#define MCF_GPIO_PTHPAR_MB_D4_MB_D4 (0x100)
+#define MCF_GPIO_PTHPAR_MB_D4_SDA1 (0x200)
+#define MCF_GPIO_PTHPAR_PTHPAR5(x) (((x)&0x3)<<0xA)
+#define MCF_GPIO_PTHPAR_MB_D5_GPIO (0)
+#define MCF_GPIO_PTHPAR_MB_D5_MB_D5 (0x400)
+#define MCF_GPIO_PTHPAR_MB_D5_SCL1 (0x800)
+#define MCF_GPIO_PTHPAR_PTHPAR6(x) (((x)&0x3)<<0xC)
+#define MCF_GPIO_PTHPAR_MB_D6_GPIO (0)
+#define MCF_GPIO_PTHPAR_MB_D6_MB_D6 (0x1000)
+#define MCF_GPIO_PTHPAR_MB_D6_CANTX (0x2000)
+#define MCF_GPIO_PTHPAR_PTHPAR7(x) (((x)&0x3)<<0xE)
+#define MCF_GPIO_PTHPAR_MB_D7_GPIO (0)
+#define MCF_GPIO_PTHPAR_MB_D7_MB_D7 (0x4000)
+#define MCF_GPIO_PTHPAR_MB_D7_CANRX (0x8000)
+
+/* Bit definitions and macros for MCF_GPIO_PORTTI */
+#define MCF_GPIO_PORTTI_PORTTI0 (0x1)
+#define MCF_GPIO_PORTTI_PORTTI1 (0x2)
+#define MCF_GPIO_PORTTI_PORTTI2 (0x4)
+#define MCF_GPIO_PORTTI_PORTTI3 (0x8)
+#define MCF_GPIO_PORTTI_PORTTI4 (0x10)
+#define MCF_GPIO_PORTTI_PORTTI5 (0x20)
+#define MCF_GPIO_PORTTI_PORTTI6 (0x40)
+#define MCF_GPIO_PORTTI_PORTTI7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_DDRTI */
+#define MCF_GPIO_DDRTI_DDRTI0 (0x1)
+#define MCF_GPIO_DDRTI_DDRTI1 (0x2)
+#define MCF_GPIO_DDRTI_DDRTI2 (0x4)
+#define MCF_GPIO_DDRTI_DDRTI3 (0x8)
+#define MCF_GPIO_DDRTI_DDRTI4 (0x10)
+#define MCF_GPIO_DDRTI_DDRTI5 (0x20)
+#define MCF_GPIO_DDRTI_DDRTI6 (0x40)
+#define MCF_GPIO_DDRTI_DDRTI7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_SETTI */
+#define MCF_GPIO_SETTI_SETTI0 (0x1)
+#define MCF_GPIO_SETTI_SETTI1 (0x2)
+#define MCF_GPIO_SETTI_SETTI2 (0x4)
+#define MCF_GPIO_SETTI_SETTI3 (0x8)
+#define MCF_GPIO_SETTI_SETTI4 (0x10)
+#define MCF_GPIO_SETTI_SETTI5 (0x20)
+#define MCF_GPIO_SETTI_SETTI6 (0x40)
+#define MCF_GPIO_SETTI_SETTI7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_CLRTI */
+#define MCF_GPIO_CLRTI_CLRTI0 (0x1)
+#define MCF_GPIO_CLRTI_CLRTI1 (0x2)
+#define MCF_GPIO_CLRTI_CLRTI2 (0x4)
+#define MCF_GPIO_CLRTI_CLRTI3 (0x8)
+#define MCF_GPIO_CLRTI_CLRTI4 (0x10)
+#define MCF_GPIO_CLRTI_CLRTI5 (0x20)
+#define MCF_GPIO_CLRTI_CLRTI6 (0x40)
+#define MCF_GPIO_CLRTI_CLRTI7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PTIPAR */
+#define MCF_GPIO_PTIPAR_PTIPAR0 (0x1)
+#define MCF_GPIO_PTIPAR_FEC_COL_GPIO (0)
+#define MCF_GPIO_PTIPAR_FEC_COL_FEC_COL (0x1)
+#define MCF_GPIO_PTIPAR_PTIPAR1 (0x2)
+#define MCF_GPIO_PTIPAR_FEC_CRS_GPIO (0)
+#define MCF_GPIO_PTIPAR_FEC_CRS_FEC_CRS (0x2)
+#define MCF_GPIO_PTIPAR_PTIPAR2 (0x4)
+#define MCF_GPIO_PTIPAR_FEC_RXCLK_GPIO (0)
+#define MCF_GPIO_PTIPAR_FEC_RXCLK_FEC_RXCLK (0x4)
+#define MCF_GPIO_PTIPAR_PTIPAR3 (0x8)
+#define MCF_GPIO_PTIPAR_FEC_RXD0_GPIO (0)
+#define MCF_GPIO_PTIPAR_FEC_RXD0_FEC_RXD0 (0x8)
+#define MCF_GPIO_PTIPAR_PTIPAR4 (0x10)
+#define MCF_GPIO_PTIPAR_FEC_RXD1_GPIO (0)
+#define MCF_GPIO_PTIPAR_FEC_RXD1_FEC_RXD1 (0x10)
+#define MCF_GPIO_PTIPAR_PTIPAR5 (0x20)
+#define MCF_GPIO_PTIPAR_FEC_RXD2_GPIO (0)
+#define MCF_GPIO_PTIPAR_FEC_RXD2_FEC_RXD2 (0x20)
+#define MCF_GPIO_PTIPAR_PTIPAR6 (0x40)
+#define MCF_GPIO_PTIPAR_FEC_RXD3_GPIO (0)
+#define MCF_GPIO_PTIPAR_FEC_RXD3_FEC_RXD3 (0x40)
+#define MCF_GPIO_PTIPAR_PTIPAR7 (0x80)
+#define MCF_GPIO_PTIPAR_FEC_RXDV_GPIO (0)
+#define MCF_GPIO_PTIPAR_FEC_RXDV_FEC_RXDV (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PORTTJ */
+#define MCF_GPIO_PORTTJ_PORTTJ0 (0x1)
+#define MCF_GPIO_PORTTJ_PORTTJ1 (0x2)
+#define MCF_GPIO_PORTTJ_PORTTJ2 (0x4)
+#define MCF_GPIO_PORTTJ_PORTTJ3 (0x8)
+#define MCF_GPIO_PORTTJ_PORTTJ4 (0x10)
+#define MCF_GPIO_PORTTJ_PORTTJ5 (0x20)
+#define MCF_GPIO_PORTTJ_PORTTJ6 (0x40)
+#define MCF_GPIO_PORTTJ_PORTTJ7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_DDRTJ */
+#define MCF_GPIO_DDRTJ_DDRTJ0 (0x1)
+#define MCF_GPIO_DDRTJ_DDRTJ1 (0x2)
+#define MCF_GPIO_DDRTJ_DDRTJ2 (0x4)
+#define MCF_GPIO_DDRTJ_DDRTJ3 (0x8)
+#define MCF_GPIO_DDRTJ_DDRTJ4 (0x10)
+#define MCF_GPIO_DDRTJ_DDRTJ5 (0x20)
+#define MCF_GPIO_DDRTJ_DDRTJ6 (0x40)
+#define MCF_GPIO_DDRTJ_DDRTJ7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_SETTJ */
+#define MCF_GPIO_SETTJ_SETTJ0 (0x1)
+#define MCF_GPIO_SETTJ_SETTJ1 (0x2)
+#define MCF_GPIO_SETTJ_SETTJ2 (0x4)
+#define MCF_GPIO_SETTJ_SETTJ3 (0x8)
+#define MCF_GPIO_SETTJ_SETTJ4 (0x10)
+#define MCF_GPIO_SETTJ_SETTJ5 (0x20)
+#define MCF_GPIO_SETTJ_SETTJ6 (0x40)
+#define MCF_GPIO_SETTJ_SETTJ7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_CLRTJ */
+#define MCF_GPIO_CLRTJ_CLRTJ0 (0x1)
+#define MCF_GPIO_CLRTJ_CLRTJ1 (0x2)
+#define MCF_GPIO_CLRTJ_CLRTJ2 (0x4)
+#define MCF_GPIO_CLRTJ_CLRTJ3 (0x8)
+#define MCF_GPIO_CLRTJ_CLRTJ4 (0x10)
+#define MCF_GPIO_CLRTJ_CLRTJ5 (0x20)
+#define MCF_GPIO_CLRTJ_CLRTJ6 (0x40)
+#define MCF_GPIO_CLRTJ_CLRTJ7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PTJPAR */
+#define MCF_GPIO_PTJPAR_PTJPAR0 (0x1)
+#define MCF_GPIO_PTJPAR_FEC_RXER_GPIO (0)
+#define MCF_GPIO_PTJPAR_FEC_RXER_FEC_RXER (0x1)
+#define MCF_GPIO_PTJPAR_PTJPAR1 (0x2)
+#define MCF_GPIO_PTJPAR_FEC_TXCLK_GPIO (0)
+#define MCF_GPIO_PTJPAR_FEC_TXCLK_FEC_TXCLK (0x2)
+#define MCF_GPIO_PTJPAR_PTJPAR2 (0x4)
+#define MCF_GPIO_PTJPAR_FEC_TXD0_GPIO (0)
+#define MCF_GPIO_PTJPAR_FEC_TXD0_FEC_TXD0 (0x4)
+#define MCF_GPIO_PTJPAR_PTJPAR3 (0x8)
+#define MCF_GPIO_PTJPAR_FEC_TXD1_GPIO (0)
+#define MCF_GPIO_PTJPAR_FEC_TXD1_FEC_TXD1 (0x8)
+#define MCF_GPIO_PTJPAR_PTJPAR4 (0x10)
+#define MCF_GPIO_PTJPAR_FEC_TXD2_GPIO (0)
+#define MCF_GPIO_PTJPAR_FEC_TXD2_FEC_TXD2 (0x10)
+#define MCF_GPIO_PTJPAR_PTJPAR5 (0x20)
+#define MCF_GPIO_PTJPAR_FEC_TXD3_GPIO (0)
+#define MCF_GPIO_PTJPAR_FEC_TXD3_FEC_TXD3 (0x20)
+#define MCF_GPIO_PTJPAR_PTJPAR6 (0x40)
+#define MCF_GPIO_PTJPAR_FEC_TXEN_GPIO (0)
+#define MCF_GPIO_PTJPAR_FEC_TXEN_FEC_TXEN (0x40)
+#define MCF_GPIO_PTJPAR_PTJPAR7 (0x80)
+#define MCF_GPIO_PTJPAR_FEC_TXER_GPIO (0)
+#define MCF_GPIO_PTJPAR_FEC_TXER_FEC_TXER (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PORTNQ */
+#define MCF_GPIO_PORTNQ_PORTNQ1 (0x2)
+#define MCF_GPIO_PORTNQ_PORTNQ2 (0x4)
+#define MCF_GPIO_PORTNQ_PORTNQ3 (0x8)
+#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10)
+#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20)
+#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40)
+#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_DDRNQ */
+#define MCF_GPIO_DDRNQ_DDRNQ1 (0x2)
+#define MCF_GPIO_DDRNQ_DDRNQ2 (0x4)
+#define MCF_GPIO_DDRNQ_DDRNQ3 (0x8)
+#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10)
+#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20)
+#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40)
+#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_SETNQ */
+#define MCF_GPIO_SETNQ_SETNQ1 (0x2)
+#define MCF_GPIO_SETNQ_SETNQ2 (0x4)
+#define MCF_GPIO_SETNQ_SETNQ3 (0x8)
+#define MCF_GPIO_SETNQ_SETNQ4 (0x10)
+#define MCF_GPIO_SETNQ_SETNQ5 (0x20)
+#define MCF_GPIO_SETNQ_SETNQ6 (0x40)
+#define MCF_GPIO_SETNQ_SETNQ7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_CLRNQ */
+#define MCF_GPIO_CLRNQ_CLRNQ1 (0x2)
+#define MCF_GPIO_CLRNQ_CLRNQ2 (0x4)
+#define MCF_GPIO_CLRNQ_CLRNQ3 (0x8)
+#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10)
+#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20)
+#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40)
+#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PNQPAR */
+#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x3)<<0x2)
+#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0)
+#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x4)
+#define MCF_GPIO_PNQPAR_IRQ1_USB_ALT_CLK (0xC)
+#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x3)<<0x4)
+#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x3)<<0x6)
+#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0)
+#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x40)
+#define MCF_GPIO_PNQPAR_IRQ3_FEC_MDIO (0x80)
+#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x3)<<0x8)
+#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x3)<<0xA)
+#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0)
+#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x400)
+#define MCF_GPIO_PNQPAR_IRQ5_FEC_MDC (0x800)
+#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x3)<<0xC)
+#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x3)<<0xE)
+#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0)
+#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000)
+
+/* Bit definitions and macros for MCF_GPIO_PORTAN */
+#define MCF_GPIO_PORTAN_PORTAN0 (0x1)
+#define MCF_GPIO_PORTAN_PORTAN1 (0x2)
+#define MCF_GPIO_PORTAN_PORTAN2 (0x4)
+#define MCF_GPIO_PORTAN_PORTAN3 (0x8)
+#define MCF_GPIO_PORTAN_PORTAN4 (0x10)
+#define MCF_GPIO_PORTAN_PORTAN5 (0x20)
+#define MCF_GPIO_PORTAN_PORTAN6 (0x40)
+#define MCF_GPIO_PORTAN_PORTAN7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_DDRAN */
+#define MCF_GPIO_DDRAN_DDRAN0 (0x1)
+#define MCF_GPIO_DDRAN_DDRAN1 (0x2)
+#define MCF_GPIO_DDRAN_DDRAN2 (0x4)
+#define MCF_GPIO_DDRAN_DDRAN3 (0x8)
+#define MCF_GPIO_DDRAN_DDRAN4 (0x10)
+#define MCF_GPIO_DDRAN_DDRAN5 (0x20)
+#define MCF_GPIO_DDRAN_DDRAN6 (0x40)
+#define MCF_GPIO_DDRAN_DDRAN7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_SETAN */
+#define MCF_GPIO_SETAN_SETAN0 (0x1)
+#define MCF_GPIO_SETAN_SETAN1 (0x2)
+#define MCF_GPIO_SETAN_SETAN2 (0x4)
+#define MCF_GPIO_SETAN_SETAN3 (0x8)
+#define MCF_GPIO_SETAN_SETAN4 (0x10)
+#define MCF_GPIO_SETAN_SETAN5 (0x20)
+#define MCF_GPIO_SETAN_SETAN6 (0x40)
+#define MCF_GPIO_SETAN_SETAN7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_CLRAN */
+#define MCF_GPIO_CLRAN_CLRAN0 (0x1)
+#define MCF_GPIO_CLRAN_CLRAN1 (0x2)
+#define MCF_GPIO_CLRAN_CLRAN2 (0x4)
+#define MCF_GPIO_CLRAN_CLRAN3 (0x8)
+#define MCF_GPIO_CLRAN_CLRAN4 (0x10)
+#define MCF_GPIO_CLRAN_CLRAN5 (0x20)
+#define MCF_GPIO_CLRAN_CLRAN6 (0x40)
+#define MCF_GPIO_CLRAN_CLRAN7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PANPAR */
+#define MCF_GPIO_PANPAR_PANPAR0 (0x1)
+#define MCF_GPIO_PANPAR_AN0_GPIO (0)
+#define MCF_GPIO_PANPAR_AN0_AN0 (0x1)
+#define MCF_GPIO_PANPAR_PANPAR1 (0x2)
+#define MCF_GPIO_PANPAR_AN1_GPIO (0)
+#define MCF_GPIO_PANPAR_AN1_AN1 (0x2)
+#define MCF_GPIO_PANPAR_PANPAR2 (0x4)
+#define MCF_GPIO_PANPAR_AN2_GPIO (0)
+#define MCF_GPIO_PANPAR_AN2_AN2 (0x4)
+#define MCF_GPIO_PANPAR_PANPAR3 (0x8)
+#define MCF_GPIO_PANPAR_AN3_GPIO (0)
+#define MCF_GPIO_PANPAR_AN3_AN3 (0x8)
+#define MCF_GPIO_PANPAR_PANPAR4 (0x10)
+#define MCF_GPIO_PANPAR_AN4_GPIO (0)
+#define MCF_GPIO_PANPAR_AN4_AN4 (0x10)
+#define MCF_GPIO_PANPAR_PANPAR5 (0x20)
+#define MCF_GPIO_PANPAR_AN5_GPIO (0)
+#define MCF_GPIO_PANPAR_AN5_AN5 (0x20)
+#define MCF_GPIO_PANPAR_PANPAR6 (0x40)
+#define MCF_GPIO_PANPAR_AN6_GPIO (0)
+#define MCF_GPIO_PANPAR_AN6_AN6 (0x40)
+#define MCF_GPIO_PANPAR_PANPAR7 (0x80)
+#define MCF_GPIO_PANPAR_AN7_GPIO (0)
+#define MCF_GPIO_PANPAR_AN7_AN7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PORTAS */
+#define MCF_GPIO_PORTAS_PORTAS0 (0x1)
+#define MCF_GPIO_PORTAS_PORTAS1 (0x2)
+#define MCF_GPIO_PORTAS_PORTAS2 (0x4)
+
+/* Bit definitions and macros for MCF_GPIO_DDRAS */
+#define MCF_GPIO_DDRAS_DDRAS0 (0x1)
+#define MCF_GPIO_DDRAS_DDRAS1 (0x2)
+#define MCF_GPIO_DDRAS_DDRAS2 (0x4)
+
+/* Bit definitions and macros for MCF_GPIO_SETAS */
+#define MCF_GPIO_SETAS_SETAS0 (0x1)
+#define MCF_GPIO_SETAS_SETAS1 (0x2)
+#define MCF_GPIO_SETAS_SETAS2 (0x4)
+
+/* Bit definitions and macros for MCF_GPIO_CLRAS */
+#define MCF_GPIO_CLRAS_CLRAS0 (0x1)
+#define MCF_GPIO_CLRAS_CLRAS1 (0x2)
+#define MCF_GPIO_CLRAS_CLRAS2 (0x4)
+
+/* Bit definitions and macros for MCF_GPIO_PASPAR */
+#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x3)<<0)
+#define MCF_GPIO_PASPAR_SCL0_GPIO (0)
+#define MCF_GPIO_PASPAR_SCL0_SCL0 (0x1)
+#define MCF_GPIO_PASPAR_SCL0_UTXD2 (0x3)
+#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x3)<<0x2)
+#define MCF_GPIO_PASPAR_SDA0_GPIO (0)
+#define MCF_GPIO_PASPAR_SDA0_SDA0 (0x4)
+#define MCF_GPIO_PASPAR_SDA0_URXD2 (0xC)
+#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x3)<<0x4)
+#define MCF_GPIO_PASPAR_MB_ALE_GPIO (0)
+#define MCF_GPIO_PASPAR_MB_ALE_MB_ALE (0x10)
+#define MCF_GPIO_PASPAR_MB_ALE_MB_CS1 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PORTQS */
+#define MCF_GPIO_PORTQS_PORTQS0 (0x1)
+#define MCF_GPIO_PORTQS_PORTQS1 (0x2)
+#define MCF_GPIO_PORTQS_PORTQS2 (0x4)
+#define MCF_GPIO_PORTQS_PORTQS3 (0x8)
+#define MCF_GPIO_PORTQS_PORTQS4 (0x10)
+#define MCF_GPIO_PORTQS_PORTQS5 (0x20)
+#define MCF_GPIO_PORTQS_PORTQS6 (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_DDRQS */
+#define MCF_GPIO_DDRQS_DDRQS0 (0x1)
+#define MCF_GPIO_DDRQS_DDRQS1 (0x2)
+#define MCF_GPIO_DDRQS_DDRQS2 (0x4)
+#define MCF_GPIO_DDRQS_DDRQS3 (0x8)
+#define MCF_GPIO_DDRQS_DDRQS4 (0x10)
+#define MCF_GPIO_DDRQS_DDRQS5 (0x20)
+#define MCF_GPIO_DDRQS_DDRQS6 (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_SETQS */
+#define MCF_GPIO_SETQS_SETQS0 (0x1)
+#define MCF_GPIO_SETQS_SETQS1 (0x2)
+#define MCF_GPIO_SETQS_SETQS2 (0x4)
+#define MCF_GPIO_SETQS_SETQS3 (0x8)
+#define MCF_GPIO_SETQS_SETQS4 (0x10)
+#define MCF_GPIO_SETQS_SETQS5 (0x20)
+#define MCF_GPIO_SETQS_SETQS6 (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_CLRQS */
+#define MCF_GPIO_CLRQS_CLRQS0 (0x1)
+#define MCF_GPIO_CLRQS_CLRQS1 (0x2)
+#define MCF_GPIO_CLRQS_CLRQS2 (0x4)
+#define MCF_GPIO_CLRQS_CLRQS3 (0x8)
+#define MCF_GPIO_CLRQS_CLRQS4 (0x10)
+#define MCF_GPIO_CLRQS_CLRQS5 (0x20)
+#define MCF_GPIO_CLRQS_CLRQS6 (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PQSPAR */
+#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x3)<<0)
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_GPIO (0)
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_DOUT (0x1)
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_SCL1 (0x2)
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_UTXD1 (0x3)
+#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x3)<<0x2)
+#define MCF_GPIO_PQSPAR_QSPI_DIN_GPIO (0)
+#define MCF_GPIO_PQSPAR_QSPI_DIN_DIN (0x4)
+#define MCF_GPIO_PQSPAR_QSPI_DIN_SDA1 (0x8)
+#define MCF_GPIO_PQSPAR_QSPI_DIN_URXD1 (0xC)
+#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x3)<<0x4)
+#define MCF_GPIO_PQSPAR_QSPI_CLK_GPIO (0)
+#define MCF_GPIO_PQSPAR_QSPI_CLK_CLK (0x10)
+#define MCF_GPIO_PQSPAR_QSPI_CLK_SCL0 (0x20)
+#define MCF_GPIO_PQSPAR_QSPI_CLK_URTS1 (0x30)
+#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x3)<<0x6)
+#define MCF_GPIO_PQSPAR_QSPI_CS0_GPIO (0)
+#define MCF_GPIO_PQSPAR_QSPI_CS0_CS0 (0x40)
+#define MCF_GPIO_PQSPAR_QSPI_CS0_SDA0 (0x80)
+#define MCF_GPIO_PQSPAR_QSPI_CS0_UCTS1 (0xC0)
+#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x3)<<0x8)
+#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x3)<<0xA)
+#define MCF_GPIO_PQSPAR_QSPI_CS2_GPIO (0)
+#define MCF_GPIO_PQSPAR_QSPI_CS2_CS2 (0x400)
+#define MCF_GPIO_PQSPAR_QSPI_CS2_SYNCB (0x800)
+#define MCF_GPIO_PQSPAR_QSPI_CS2_USB_DM_PDOWN (0xC00)
+#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x3)<<0xC)
+#define MCF_GPIO_PQSPAR_QSPI_CS3_GPIO (0)
+#define MCF_GPIO_PQSPAR_QSPI_CS3_CS3 (0x1000)
+#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCA (0x2000)
+#define MCF_GPIO_PQSPAR_QSPI_CS3_USB_DP_PDOWN (0x3000)
+
+/* Bit definitions and macros for MCF_GPIO_PORTTA */
+#define MCF_GPIO_PORTTA_PORTTA0 (0x1)
+#define MCF_GPIO_PORTTA_PORTTA1 (0x2)
+#define MCF_GPIO_PORTTA_PORTTA2 (0x4)
+#define MCF_GPIO_PORTTA_PORTTA3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_DDRTA */
+#define MCF_GPIO_DDRTA_DDRTA0 (0x1)
+#define MCF_GPIO_DDRTA_DDRTA1 (0x2)
+#define MCF_GPIO_DDRTA_DDRTA2 (0x4)
+#define MCF_GPIO_DDRTA_DDRTA3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_SETTA */
+#define MCF_GPIO_SETTA_SETTA0 (0x1)
+#define MCF_GPIO_SETTA_SETTA1 (0x2)
+#define MCF_GPIO_SETTA_SETTA2 (0x4)
+#define MCF_GPIO_SETTA_SETTA3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_CLRTA */
+#define MCF_GPIO_CLRTA_CLRTA0 (0x1)
+#define MCF_GPIO_CLRTA_CLRTA1 (0x2)
+#define MCF_GPIO_CLRTA_CLRTA2 (0x4)
+#define MCF_GPIO_CLRTA_CLRTA3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PTAPAR */
+#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x3)<<0)
+#define MCF_GPIO_PTAPAR_ICOC0_GPIO (0)
+#define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x1)
+#define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x3)
+#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x3)<<0x2)
+#define MCF_GPIO_PTAPAR_ICOC1_GPIO (0)
+#define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x4)
+#define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0xC)
+#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x3)<<0x4)
+#define MCF_GPIO_PTAPAR_ICOC2_GPIO (0)
+#define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10)
+#define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x30)
+#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x3)<<0x6)
+#define MCF_GPIO_PTAPAR_ICOC3_GPIO (0)
+#define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40)
+#define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0xC0)
+
+/* Bit definitions and macros for MCF_GPIO_PORTTC */
+#define MCF_GPIO_PORTTC_PORTTC0 (0x1)
+#define MCF_GPIO_PORTTC_PORTTC1 (0x2)
+#define MCF_GPIO_PORTTC_PORTTC2 (0x4)
+#define MCF_GPIO_PORTTC_PORTTC3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_DDRTC */
+#define MCF_GPIO_DDRTC_DDRTC0 (0x1)
+#define MCF_GPIO_DDRTC_DDRTC1 (0x2)
+#define MCF_GPIO_DDRTC_DDRTC2 (0x4)
+#define MCF_GPIO_DDRTC_DDRTC3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_SETTC */
+#define MCF_GPIO_SETTC_SETTC0 (0x1)
+#define MCF_GPIO_SETTC_SETTC1 (0x2)
+#define MCF_GPIO_SETTC_SETTC2 (0x4)
+#define MCF_GPIO_SETTC_SETTC3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_CLRTC */
+#define MCF_GPIO_CLRTC_CLRTC0 (0x1)
+#define MCF_GPIO_CLRTC_CLRTC1 (0x2)
+#define MCF_GPIO_CLRTC_CLRTC2 (0x4)
+#define MCF_GPIO_CLRTC_CLRTC3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PTCPAR */
+#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x3)<<0)
+#define MCF_GPIO_PTCPAR_DTIN0_GPIO (0)
+#define MCF_GPIO_PTCPAR_DTIN0_DTIN0 (0x1)
+#define MCF_GPIO_PTCPAR_DTIN0_DTOUT0 (0x2)
+#define MCF_GPIO_PTCPAR_DTIN0_PWM0 (0x3)
+#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x3)<<0x2)
+#define MCF_GPIO_PTCPAR_DTIN1_GPIO (0)
+#define MCF_GPIO_PTCPAR_DTIN1_DTIN1 (0x4)
+#define MCF_GPIO_PTCPAR_DTIN1_DTOUT1 (0x8)
+#define MCF_GPIO_PTCPAR_DTIN1_PWM2 (0xC)
+#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x3)<<0x4)
+#define MCF_GPIO_PTCPAR_DTIN2_GPIO (0)
+#define MCF_GPIO_PTCPAR_DTIN2_DTIN2 (0x10)
+#define MCF_GPIO_PTCPAR_DTIN2_DTOUT2 (0x20)
+#define MCF_GPIO_PTCPAR_DTIN2_PWM4 (0x30)
+#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x3)<<0x6)
+#define MCF_GPIO_PTCPAR_DTIN3_GPIO (0)
+#define MCF_GPIO_PTCPAR_DTIN3_DTIN3 (0x40)
+#define MCF_GPIO_PTCPAR_DTIN3_DTOUT3 (0x80)
+#define MCF_GPIO_PTCPAR_DTIN3_PWM6 (0xC0)
+
+/* Bit definitions and macros for MCF_GPIO_PORTUA */
+#define MCF_GPIO_PORTUA_PORTUA0 (0x1)
+#define MCF_GPIO_PORTUA_PORTUA1 (0x2)
+#define MCF_GPIO_PORTUA_PORTUA2 (0x4)
+#define MCF_GPIO_PORTUA_PORTUA3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_DDRUA */
+#define MCF_GPIO_DDRUA_DDRUA0 (0x1)
+#define MCF_GPIO_DDRUA_DDRUA1 (0x2)
+#define MCF_GPIO_DDRUA_DDRUA2 (0x4)
+#define MCF_GPIO_DDRUA_DDRUA3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_SETUA */
+#define MCF_GPIO_SETUA_SETUA0 (0x1)
+#define MCF_GPIO_SETUA_SETUA1 (0x2)
+#define MCF_GPIO_SETUA_SETUA2 (0x4)
+#define MCF_GPIO_SETUA_SETUA3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_CLRUA */
+#define MCF_GPIO_CLRUA_CLRUA0 (0x1)
+#define MCF_GPIO_CLRUA_CLRUA1 (0x2)
+#define MCF_GPIO_CLRUA_CLRUA2 (0x4)
+#define MCF_GPIO_CLRUA_CLRUA3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PUAPAR */
+#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x3)<<0)
+#define MCF_GPIO_PUAPAR_UTXD0_GPIO (0)
+#define MCF_GPIO_PUAPAR_UTXD0_UTXD0 (0x1)
+#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x3)<<0x2)
+#define MCF_GPIO_PUAPAR_URXD0_GPIO (0)
+#define MCF_GPIO_PUAPAR_URXD0_URXD0 (0x4)
+#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x3)<<0x4)
+#define MCF_GPIO_PUAPAR_URTS0_GPIO (0)
+#define MCF_GPIO_PUAPAR_URTS0_URTS0 (0x10)
+#define MCF_GPIO_PUAPAR_URTS0_USB_VBUSD (0x30)
+#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x3)<<0x6)
+#define MCF_GPIO_PUAPAR_UCTS0_GPIO (0)
+#define MCF_GPIO_PUAPAR_UCTS0_UCTS0 (0x40)
+#define MCF_GPIO_PUAPAR_UCTS0_USB_VBUSE (0xC0)
+
+/* Bit definitions and macros for MCF_GPIO_PORTUB */
+#define MCF_GPIO_PORTUB_PORTUB0 (0x1)
+#define MCF_GPIO_PORTUB_PORTUB1 (0x2)
+#define MCF_GPIO_PORTUB_PORTUB2 (0x4)
+#define MCF_GPIO_PORTUB_PORTUB3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_DDRUB */
+#define MCF_GPIO_DDRUB_DDRUB0 (0x1)
+#define MCF_GPIO_DDRUB_DDRUB1 (0x2)
+#define MCF_GPIO_DDRUB_DDRUB2 (0x4)
+#define MCF_GPIO_DDRUB_DDRUB3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_SETUB */
+#define MCF_GPIO_SETUB_SETUB0 (0x1)
+#define MCF_GPIO_SETUB_SETUB1 (0x2)
+#define MCF_GPIO_SETUB_SETUB2 (0x4)
+#define MCF_GPIO_SETUB_SETUB3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_CLRUB */
+#define MCF_GPIO_CLRUB_CLRUB0 (0x1)
+#define MCF_GPIO_CLRUB_CLRUB1 (0x2)
+#define MCF_GPIO_CLRUB_CLRUB2 (0x4)
+#define MCF_GPIO_CLRUB_CLRUB3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PUBPAR */
+#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x3)<<0)
+#define MCF_GPIO_PUBPAR_UTXD1_GPIO (0)
+#define MCF_GPIO_PUBPAR_UTXD1_UTXD1 (0x1)
+#define MCF_GPIO_PUBPAR_UTXD1_SCL1 (0x2)
+#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x3)<<0x2)
+#define MCF_GPIO_PUBPAR_URXD1_GPIO (0)
+#define MCF_GPIO_PUBPAR_URXD1_URXD1 (0x4)
+#define MCF_GPIO_PUBPAR_URXD1_SDA1 (0x8)
+#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x3)<<0x4)
+#define MCF_GPIO_PUBPAR_URTS1_GPIO (0)
+#define MCF_GPIO_PUBPAR_URTS1_URTS1 (0x10)
+#define MCF_GPIO_PUBPAR_URTS1_SYNCB (0x20)
+#define MCF_GPIO_PUBPAR_URTS1_UTXD2 (0x30)
+#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x3)<<0x6)
+#define MCF_GPIO_PUBPAR_UCTS1_GPIO (0)
+#define MCF_GPIO_PUBPAR_UCTS1_UCTS1 (0x40)
+#define MCF_GPIO_PUBPAR_UCTS1_SYNCA (0x80)
+#define MCF_GPIO_PUBPAR_UCTS1_URXD2 (0xC0)
+
+/* Bit definitions and macros for MCF_GPIO_PORTUC */
+#define MCF_GPIO_PORTUC_PORTUC0 (0x1)
+#define MCF_GPIO_PORTUC_PORTUC1 (0x2)
+#define MCF_GPIO_PORTUC_PORTUC2 (0x4)
+#define MCF_GPIO_PORTUC_PORTUC3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_DDRUC */
+#define MCF_GPIO_DDRUC_DDRUC0 (0x1)
+#define MCF_GPIO_DDRUC_DDRUC1 (0x2)
+#define MCF_GPIO_DDRUC_DDRUC2 (0x4)
+#define MCF_GPIO_DDRUC_DDRUC3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_SETUC */
+#define MCF_GPIO_SETUC_SETUC0 (0x1)
+#define MCF_GPIO_SETUC_SETUC1 (0x2)
+#define MCF_GPIO_SETUC_SETUC2 (0x4)
+#define MCF_GPIO_SETUC_SETUC3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_CLRUC */
+#define MCF_GPIO_CLRUC_CLRUC0 (0x1)
+#define MCF_GPIO_CLRUC_CLRUC1 (0x2)
+#define MCF_GPIO_CLRUC_CLRUC2 (0x4)
+#define MCF_GPIO_CLRUC_CLRUC3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PUCPAR */
+#define MCF_GPIO_PUCPAR_PUCPAR0(x) (((x)&0x3)<<0)
+#define MCF_GPIO_PUCPAR_UTXD2_GPIO (0)
+#define MCF_GPIO_PUCPAR_UTXD2_UTXD2 (0x1)
+#define MCF_GPIO_PUCPAR_UTXD2_CANTX (0x2)
+#define MCF_GPIO_PUCPAR_PUCPAR1(x) (((x)&0x3)<<0x2)
+#define MCF_GPIO_PUCPAR_URXD2_GPIO (0)
+#define MCF_GPIO_PUCPAR_URXD2_URXD2 (0x4)
+#define MCF_GPIO_PUCPAR_URXD2_CANRX (0x8)
+#define MCF_GPIO_PUCPAR_PUCPAR2(x) (((x)&0x3)<<0x4)
+#define MCF_GPIO_PUCPAR_URTS2_GPIO (0)
+#define MCF_GPIO_PUCPAR_URTS2_URTS2 (0x10)
+#define MCF_GPIO_PUCPAR_URTS2_SDA1 (0x20)
+#define MCF_GPIO_PUCPAR_URTS2_USB_VBUSDIS (0x30)
+#define MCF_GPIO_PUCPAR_PUCPAR3(x) (((x)&0x3)<<0x6)
+#define MCF_GPIO_PUCPAR_UCTS2_GPIO (0)
+#define MCF_GPIO_PUCPAR_UCTS2_UCTS2 (0x40)
+#define MCF_GPIO_PUCPAR_UCTS2_SCL1 (0x80)
+#define MCF_GPIO_PUCPAR_UCTS2_USB_VBUSCHG (0xC0)
+
+/* Bit definitions and macros for MCF_GPIO_PORTDD */
+#define MCF_GPIO_PORTDD_PORTDD0 (0x1)
+#define MCF_GPIO_PORTDD_PORTDD1 (0x2)
+#define MCF_GPIO_PORTDD_PORTDD2 (0x4)
+#define MCF_GPIO_PORTDD_PORTDD3 (0x8)
+#define MCF_GPIO_PORTDD_PORTDD4 (0x10)
+#define MCF_GPIO_PORTDD_PORTDD5 (0x20)
+#define MCF_GPIO_PORTDD_PORTDD6 (0x40)
+#define MCF_GPIO_PORTDD_PORTDD7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_DDRDD */
+#define MCF_GPIO_DDRDD_DDRDD0 (0x1)
+#define MCF_GPIO_DDRDD_DDRDD1 (0x2)
+#define MCF_GPIO_DDRDD_DDRDD2 (0x4)
+#define MCF_GPIO_DDRDD_DDRDD3 (0x8)
+#define MCF_GPIO_DDRDD_DDRDD4 (0x10)
+#define MCF_GPIO_DDRDD_DDRDD5 (0x20)
+#define MCF_GPIO_DDRDD_DDRDD6 (0x40)
+#define MCF_GPIO_DDRDD_DDRDD7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_SETDD */
+#define MCF_GPIO_SETDD_SETDD0 (0x1)
+#define MCF_GPIO_SETDD_SETDD1 (0x2)
+#define MCF_GPIO_SETDD_SETDD2 (0x4)
+#define MCF_GPIO_SETDD_SETDD3 (0x8)
+#define MCF_GPIO_SETDD_SETDD4 (0x10)
+#define MCF_GPIO_SETDD_SETDD5 (0x20)
+#define MCF_GPIO_SETDD_SETDD6 (0x40)
+#define MCF_GPIO_SETDD_SETDD7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_CLRDD */
+#define MCF_GPIO_CLRDD_CLRDD0 (0x1)
+#define MCF_GPIO_CLRDD_CLRDD1 (0x2)
+#define MCF_GPIO_CLRDD_CLRDD2 (0x4)
+#define MCF_GPIO_CLRDD_CLRDD3 (0x8)
+#define MCF_GPIO_CLRDD_CLRDD4 (0x10)
+#define MCF_GPIO_CLRDD_CLRDD5 (0x20)
+#define MCF_GPIO_CLRDD_CLRDD6 (0x40)
+#define MCF_GPIO_CLRDD_CLRDD7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDPAR */
+#define MCF_GPIO_PDDPAR_PDDPAR0 (0x1)
+#define MCF_GPIO_PDDPAR_PST0_GPIO (0)
+#define MCF_GPIO_PDDPAR_PST0_PST0 (0x1)
+#define MCF_GPIO_PDDPAR_PDDPAR1 (0x2)
+#define MCF_GPIO_PDDPAR_PST1_GPIO (0)
+#define MCF_GPIO_PDDPAR_PST1_PST1 (0x2)
+#define MCF_GPIO_PDDPAR_PDDPAR2 (0x4)
+#define MCF_GPIO_PDDPAR_PST2_GPIO (0)
+#define MCF_GPIO_PDDPAR_PST2_PST2 (0x4)
+#define MCF_GPIO_PDDPAR_PDDPAR3 (0x8)
+#define MCF_GPIO_PDDPAR_PST3_GPIO (0)
+#define MCF_GPIO_PDDPAR_PST3_PST3 (0x8)
+#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10)
+#define MCF_GPIO_PDDPAR_DDATA0_GPIO (0)
+#define MCF_GPIO_PDDPAR_DDATA0_DDATA0 (0x10)
+#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20)
+#define MCF_GPIO_PDDPAR_DDATA1_GPIO (0)
+#define MCF_GPIO_PDDPAR_DDATA1_DDATA1 (0x20)
+#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40)
+#define MCF_GPIO_PDDPAR_DDATA2_GPIO (0)
+#define MCF_GPIO_PDDPAR_DDATA2_DDATA2 (0x40)
+#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80)
+#define MCF_GPIO_PDDPAR_DDATA3_GPIO (0)
+#define MCF_GPIO_PDDPAR_DDATA3_DDATA3 (0x80)
+
+
+#endif /* __MCF52259_GPIO_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_GPT.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_GPT.h new file mode 100644 index 00000000..c61fd982 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_GPT.h @@ -0,0 +1,206 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_GPT_H__
+#define __MCF52259_GPT_H__
+
+
+/*********************************************************************
+*
+* General Purpose Timer Module (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT_GPTIOS (*(vuint8 *)(0x401A0000))
+#define MCF_GPT_GPTCFORC (*(vuint8 *)(0x401A0001))
+#define MCF_GPT_GPTOC3M (*(vuint8 *)(0x401A0002))
+#define MCF_GPT_GPTOC3D (*(vuint8 *)(0x401A0003))
+#define MCF_GPT_GPTCNT (*(vuint16*)(0x401A0004))
+#define MCF_GPT_GPTSCR1 (*(vuint8 *)(0x401A0006))
+#define MCF_GPT_GPTTOV (*(vuint8 *)(0x401A0008))
+#define MCF_GPT_GPTCTL1 (*(vuint8 *)(0x401A0009))
+#define MCF_GPT_GPTCTL2 (*(vuint8 *)(0x401A000B))
+#define MCF_GPT_GPTIE (*(vuint8 *)(0x401A000C))
+#define MCF_GPT_GPTSCR2 (*(vuint8 *)(0x401A000D))
+#define MCF_GPT_GPTFLG1 (*(vuint8 *)(0x401A000E))
+#define MCF_GPT_GPTFLG2 (*(vuint8 *)(0x401A000F))
+#define MCF_GPT_GPTC0 (*(vuint16*)(0x401A0010))
+#define MCF_GPT_GPTC1 (*(vuint16*)(0x401A0012))
+#define MCF_GPT_GPTC2 (*(vuint16*)(0x401A0014))
+#define MCF_GPT_GPTC3 (*(vuint16*)(0x401A0016))
+#define MCF_GPT_GPTPACTL (*(vuint8 *)(0x401A0018))
+#define MCF_GPT_GPTPAFLG (*(vuint8 *)(0x401A0019))
+#define MCF_GPT_GPTPACNT (*(vuint16*)(0x401A001A))
+#define MCF_GPT_GPTPORT (*(vuint8 *)(0x401A001D))
+#define MCF_GPT_GPTDDR (*(vuint8 *)(0x401A001E))
+#define MCF_GPT_GPTC(x) (*(vuint16*)(0x401A0010 + ((x)*0x2)))
+
+
+/* Bit definitions and macros for MCF_GPT_GPTIOS */
+#define MCF_GPT_GPTIOS_IOS0 (0x1)
+#define MCF_GPT_GPTIOS_IOS1 (0x2)
+#define MCF_GPT_GPTIOS_IOS2 (0x4)
+#define MCF_GPT_GPTIOS_IOS3 (0x8)
+
+/* Bit definitions and macros for MCF_GPT_GPTCFORC */
+#define MCF_GPT_GPTCFORC_FOC0 (0x1)
+#define MCF_GPT_GPTCFORC_FOC1 (0x2)
+#define MCF_GPT_GPTCFORC_FOC2 (0x4)
+#define MCF_GPT_GPTCFORC_FOC3 (0x8)
+
+/* Bit definitions and macros for MCF_GPT_GPTOC3M */
+#define MCF_GPT_GPTOC3M_OC3M0 (0x1)
+#define MCF_GPT_GPTOC3M_OC3M1 (0x2)
+#define MCF_GPT_GPTOC3M_OC3M2 (0x4)
+#define MCF_GPT_GPTOC3M_OC3M3 (0x8)
+
+/* Bit definitions and macros for MCF_GPT_GPTOC3D */
+#define MCF_GPT_GPTOC3D_OC3D0 (0x1)
+#define MCF_GPT_GPTOC3D_OC3D1 (0x2)
+#define MCF_GPT_GPTOC3D_OC3D2 (0x4)
+#define MCF_GPT_GPTOC3D_OC3D3 (0x8)
+
+/* Bit definitions and macros for MCF_GPT_GPTCNT */
+#define MCF_GPT_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_GPT_GPTSCR1 */
+#define MCF_GPT_GPTSCR1_TFFCA (0x10)
+#define MCF_GPT_GPTSCR1_GPTEN (0x80)
+
+/* Bit definitions and macros for MCF_GPT_GPTTOV */
+#define MCF_GPT_GPTTOV_TOV0 (0x1)
+#define MCF_GPT_GPTTOV_TOV1 (0x2)
+#define MCF_GPT_GPTTOV_TOV2 (0x4)
+#define MCF_GPT_GPTTOV_TOV3 (0x8)
+
+/* Bit definitions and macros for MCF_GPT_GPTCTL1 */
+#define MCF_GPT_GPTCTL1_OL0 (0x1)
+#define MCF_GPT_GPTCTL1_OM0 (0x2)
+#define MCF_GPT_GPTCTL1_OL1 (0x4)
+#define MCF_GPT_GPTCTL1_OM1 (0x8)
+#define MCF_GPT_GPTCTL1_OL2 (0x10)
+#define MCF_GPT_GPTCTL1_OM2 (0x20)
+#define MCF_GPT_GPTCTL1_OL3 (0x40)
+#define MCF_GPT_GPTCTL1_OM3 (0x80)
+#define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING (0)
+#define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE (0x1)
+#define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR (0x2)
+#define MCF_GPT_GPTCTL1_OUTPUT0_SET (0x3)
+#define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING (0)
+#define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE (0x4)
+#define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR (0x8)
+#define MCF_GPT_GPTCTL1_OUTPUT1_SET (0xC)
+#define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING (0)
+#define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE (0x10)
+#define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR (0x20)
+#define MCF_GPT_GPTCTL1_OUTPUT2_SET (0x30)
+#define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING (0)
+#define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE (0x40)
+#define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR (0x80)
+#define MCF_GPT_GPTCTL1_OUTPUT3_SET (0xC0)
+
+/* Bit definitions and macros for MCF_GPT_GPTCTL2 */
+#define MCF_GPT_GPTCTL2_EDG0A (0x1)
+#define MCF_GPT_GPTCTL2_EDG0B (0x2)
+#define MCF_GPT_GPTCTL2_EDG1A (0x4)
+#define MCF_GPT_GPTCTL2_EDG1B (0x8)
+#define MCF_GPT_GPTCTL2_EDG2A (0x10)
+#define MCF_GPT_GPTCTL2_EDG2B (0x20)
+#define MCF_GPT_GPTCTL2_EDG3A (0x40)
+#define MCF_GPT_GPTCTL2_EDG3B (0x80)
+#define MCF_GPT_GPTCTL2_INPUT0_DISABLED (0)
+#define MCF_GPT_GPTCTL2_INPUT0_RISING (0x1)
+#define MCF_GPT_GPTCTL2_INPUT0_FALLING (0x2)
+#define MCF_GPT_GPTCTL2_INPUT0_ANY (0x3)
+#define MCF_GPT_GPTCTL2_INPUT1_DISABLED (0)
+#define MCF_GPT_GPTCTL2_INPUT1_RISING (0x4)
+#define MCF_GPT_GPTCTL2_INPUT1_FALLING (0x8)
+#define MCF_GPT_GPTCTL2_INPUT1_ANY (0xC)
+#define MCF_GPT_GPTCTL2_INPUT2_DISABLED (0)
+#define MCF_GPT_GPTCTL2_INPUT2_RISING (0x10)
+#define MCF_GPT_GPTCTL2_INPUT2_FALLING (0x20)
+#define MCF_GPT_GPTCTL2_INPUT2_ANY (0x30)
+#define MCF_GPT_GPTCTL2_INPUT3_DISABLED (0)
+#define MCF_GPT_GPTCTL2_INPUT3_RISING (0x40)
+#define MCF_GPT_GPTCTL2_INPUT3_FALLING (0x80)
+#define MCF_GPT_GPTCTL2_INPUT3_ANY (0xC0)
+
+/* Bit definitions and macros for MCF_GPT_GPTIE */
+#define MCF_GPT_GPTIE_CI0 (0x1)
+#define MCF_GPT_GPTIE_CI1 (0x2)
+#define MCF_GPT_GPTIE_CI2 (0x4)
+#define MCF_GPT_GPTIE_CI3 (0x8)
+
+/* Bit definitions and macros for MCF_GPT_GPTSCR2 */
+#define MCF_GPT_GPTSCR2_PR(x) (((x)&0x7)<<0)
+#define MCF_GPT_GPTSCR2_PR_1 (0)
+#define MCF_GPT_GPTSCR2_PR_2 (0x1)
+#define MCF_GPT_GPTSCR2_PR_4 (0x2)
+#define MCF_GPT_GPTSCR2_PR_8 (0x3)
+#define MCF_GPT_GPTSCR2_PR_16 (0x4)
+#define MCF_GPT_GPTSCR2_PR_32 (0x5)
+#define MCF_GPT_GPTSCR2_PR_64 (0x6)
+#define MCF_GPT_GPTSCR2_PR_128 (0x7)
+#define MCF_GPT_GPTSCR2_TCRE (0x8)
+#define MCF_GPT_GPTSCR2_RDPT (0x10)
+#define MCF_GPT_GPTSCR2_PUPT (0x20)
+#define MCF_GPT_GPTSCR2_TOI (0x80)
+
+/* Bit definitions and macros for MCF_GPT_GPTFLG1 */
+#define MCF_GPT_GPTFLG1_CF0 (0x1)
+#define MCF_GPT_GPTFLG1_CF1 (0x2)
+#define MCF_GPT_GPTFLG1_CF2 (0x4)
+#define MCF_GPT_GPTFLG1_CF3 (0x8)
+
+/* Bit definitions and macros for MCF_GPT_GPTFLG2 */
+#define MCF_GPT_GPTFLG2_TOF (0x80)
+
+/* Bit definitions and macros for MCF_GPT_GPTC */
+#define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_GPT_GPTPACTL */
+#define MCF_GPT_GPTPACTL_PAI (0x1)
+#define MCF_GPT_GPTPACTL_PAOVI (0x2)
+#define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)
+#define MCF_GPT_GPTPACTL_CLK_GPTPR (0)
+#define MCF_GPT_GPTPACTL_CLK_PACLK (0x1)
+#define MCF_GPT_GPTPACTL_CLK_PACLK_256 (0x2)
+#define MCF_GPT_GPTPACTL_CLK_PACLK_65536 (0x3)
+#define MCF_GPT_GPTPACTL_PEDGE (0x10)
+#define MCF_GPT_GPTPACTL_PAMOD (0x20)
+#define MCF_GPT_GPTPACTL_PAE (0x40)
+
+/* Bit definitions and macros for MCF_GPT_GPTPAFLG */
+#define MCF_GPT_GPTPAFLG_PAIF (0x1)
+#define MCF_GPT_GPTPAFLG_PAOVF (0x2)
+
+/* Bit definitions and macros for MCF_GPT_GPTPACNT */
+#define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_GPT_GPTPORT */
+#define MCF_GPT_GPTPORT_PORTT0 (0x1)
+#define MCF_GPT_GPTPORT_PORTT1 (0x2)
+#define MCF_GPT_GPTPORT_PORTT2 (0x4)
+#define MCF_GPT_GPTPORT_PORTT3 (0x8)
+
+/* Bit definitions and macros for MCF_GPT_GPTDDR */
+#define MCF_GPT_GPTDDR_DDRT0 (0x1)
+#define MCF_GPT_GPTDDR_DDRT1 (0x2)
+#define MCF_GPT_GPTDDR_DDRT2 (0x4)
+#define MCF_GPT_GPTDDR_DDRT3 (0x8)
+
+
+#endif /* __MCF52259_GPT_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_I2C.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_I2C.h new file mode 100644 index 00000000..875f4d64 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_I2C.h @@ -0,0 +1,73 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_I2C_H__
+#define __MCF52259_I2C_H__
+
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C0_I2ADR (*(vuint8 *)(0x40000300))
+#define MCF_I2C0_I2FDR (*(vuint8 *)(0x40000304))
+#define MCF_I2C0_I2CR (*(vuint8 *)(0x40000308))
+#define MCF_I2C0_I2SR (*(vuint8 *)(0x4000030C))
+#define MCF_I2C0_I2DR (*(vuint8 *)(0x40000310))
+
+#define MCF_I2C1_I2ADR (*(vuint8 *)(0x40000380))
+#define MCF_I2C1_I2FDR (*(vuint8 *)(0x40000384))
+#define MCF_I2C1_I2CR (*(vuint8 *)(0x40000388))
+#define MCF_I2C1_I2SR (*(vuint8 *)(0x4000038C))
+#define MCF_I2C1_I2DR (*(vuint8 *)(0x40000390))
+
+#define MCF_I2C_I2ADR(x) (*(vuint8 *)(0x40000300 + ((x)*0x80)))
+#define MCF_I2C_I2FDR(x) (*(vuint8 *)(0x40000304 + ((x)*0x80)))
+#define MCF_I2C_I2CR(x) (*(vuint8 *)(0x40000308 + ((x)*0x80)))
+#define MCF_I2C_I2SR(x) (*(vuint8 *)(0x4000030C + ((x)*0x80)))
+#define MCF_I2C_I2DR(x) (*(vuint8 *)(0x40000310 + ((x)*0x80)))
+
+
+/* Bit definitions and macros for MCF_I2C_I2ADR */
+#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA (0x4)
+#define MCF_I2C_I2CR_TXAK (0x8)
+#define MCF_I2C_I2CR_MTX (0x10)
+#define MCF_I2C_I2CR_MSTA (0x20)
+#define MCF_I2C_I2CR_IIEN (0x40)
+#define MCF_I2C_I2CR_IEN (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK (0x1)
+#define MCF_I2C_I2SR_IIF (0x2)
+#define MCF_I2C_I2SR_SRW (0x4)
+#define MCF_I2C_I2SR_IAL (0x10)
+#define MCF_I2C_I2SR_IBB (0x20)
+#define MCF_I2C_I2SR_IAAS (0x40)
+#define MCF_I2C_I2SR_ICF (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2DR */
+#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
+
+
+#endif /* __MCF52259_I2C_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_INTC.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_INTC.h new file mode 100644 index 00000000..c3a68143 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_INTC.h @@ -0,0 +1,492 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_INTC_H__
+#define __MCF52259_INTC_H__
+
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC0_IPRH (*(vuint32*)(0x40000C00))
+#define MCF_INTC0_IPRL (*(vuint32*)(0x40000C04))
+#define MCF_INTC0_IMRH (*(vuint32*)(0x40000C08))
+#define MCF_INTC0_IMRL (*(vuint32*)(0x40000C0C))
+#define MCF_INTC0_INTFRCH (*(vuint32*)(0x40000C10))
+#define MCF_INTC0_INTFRCL (*(vuint32*)(0x40000C14))
+#define MCF_INTC0_IRLR (*(vuint8 *)(0x40000C18))
+#define MCF_INTC0_IACKLPR (*(vuint8 *)(0x40000C19))
+#define MCF_INTC0_ICR01 (*(vuint8 *)(0x40000C41))
+#define MCF_INTC0_ICR02 (*(vuint8 *)(0x40000C42))
+#define MCF_INTC0_ICR03 (*(vuint8 *)(0x40000C43))
+#define MCF_INTC0_ICR04 (*(vuint8 *)(0x40000C44))
+#define MCF_INTC0_ICR05 (*(vuint8 *)(0x40000C45))
+#define MCF_INTC0_ICR06 (*(vuint8 *)(0x40000C46))
+#define MCF_INTC0_ICR07 (*(vuint8 *)(0x40000C47))
+#define MCF_INTC0_ICR08 (*(vuint8 *)(0x40000C48))
+#define MCF_INTC0_ICR09 (*(vuint8 *)(0x40000C49))
+#define MCF_INTC0_ICR10 (*(vuint8 *)(0x40000C4A))
+#define MCF_INTC0_ICR11 (*(vuint8 *)(0x40000C4B))
+#define MCF_INTC0_ICR12 (*(vuint8 *)(0x40000C4C))
+#define MCF_INTC0_ICR13 (*(vuint8 *)(0x40000C4D))
+#define MCF_INTC0_ICR14 (*(vuint8 *)(0x40000C4E))
+#define MCF_INTC0_ICR15 (*(vuint8 *)(0x40000C4F))
+#define MCF_INTC0_ICR16 (*(vuint8 *)(0x40000C50))
+#define MCF_INTC0_ICR17 (*(vuint8 *)(0x40000C51))
+#define MCF_INTC0_ICR18 (*(vuint8 *)(0x40000C52))
+#define MCF_INTC0_ICR19 (*(vuint8 *)(0x40000C53))
+#define MCF_INTC0_ICR20 (*(vuint8 *)(0x40000C54))
+#define MCF_INTC0_ICR21 (*(vuint8 *)(0x40000C55))
+#define MCF_INTC0_ICR22 (*(vuint8 *)(0x40000C56))
+#define MCF_INTC0_ICR23 (*(vuint8 *)(0x40000C57))
+#define MCF_INTC0_ICR24 (*(vuint8 *)(0x40000C58))
+#define MCF_INTC0_ICR25 (*(vuint8 *)(0x40000C59))
+#define MCF_INTC0_ICR26 (*(vuint8 *)(0x40000C5A))
+#define MCF_INTC0_ICR27 (*(vuint8 *)(0x40000C5B))
+#define MCF_INTC0_ICR28 (*(vuint8 *)(0x40000C5C))
+#define MCF_INTC0_ICR29 (*(vuint8 *)(0x40000C5D))
+#define MCF_INTC0_ICR30 (*(vuint8 *)(0x40000C5E))
+#define MCF_INTC0_ICR31 (*(vuint8 *)(0x40000C5F))
+#define MCF_INTC0_ICR32 (*(vuint8 *)(0x40000C60))
+#define MCF_INTC0_ICR33 (*(vuint8 *)(0x40000C61))
+#define MCF_INTC0_ICR34 (*(vuint8 *)(0x40000C62))
+#define MCF_INTC0_ICR35 (*(vuint8 *)(0x40000C63))
+#define MCF_INTC0_ICR36 (*(vuint8 *)(0x40000C64))
+#define MCF_INTC0_ICR37 (*(vuint8 *)(0x40000C65))
+#define MCF_INTC0_ICR38 (*(vuint8 *)(0x40000C66))
+#define MCF_INTC0_ICR39 (*(vuint8 *)(0x40000C67))
+#define MCF_INTC0_ICR40 (*(vuint8 *)(0x40000C68))
+#define MCF_INTC0_ICR41 (*(vuint8 *)(0x40000C69))
+#define MCF_INTC0_ICR42 (*(vuint8 *)(0x40000C6A))
+#define MCF_INTC0_ICR43 (*(vuint8 *)(0x40000C6B))
+#define MCF_INTC0_ICR44 (*(vuint8 *)(0x40000C6C))
+#define MCF_INTC0_ICR45 (*(vuint8 *)(0x40000C6D))
+#define MCF_INTC0_ICR46 (*(vuint8 *)(0x40000C6E))
+#define MCF_INTC0_ICR47 (*(vuint8 *)(0x40000C6F))
+#define MCF_INTC0_ICR48 (*(vuint8 *)(0x40000C70))
+#define MCF_INTC0_ICR49 (*(vuint8 *)(0x40000C71))
+#define MCF_INTC0_ICR50 (*(vuint8 *)(0x40000C72))
+#define MCF_INTC0_ICR51 (*(vuint8 *)(0x40000C73))
+#define MCF_INTC0_ICR52 (*(vuint8 *)(0x40000C74))
+#define MCF_INTC0_ICR53 (*(vuint8 *)(0x40000C75))
+#define MCF_INTC0_ICR54 (*(vuint8 *)(0x40000C76))
+#define MCF_INTC0_ICR55 (*(vuint8 *)(0x40000C77))
+#define MCF_INTC0_ICR56 (*(vuint8 *)(0x40000C78))
+#define MCF_INTC0_ICR57 (*(vuint8 *)(0x40000C79))
+#define MCF_INTC0_ICR58 (*(vuint8 *)(0x40000C7A))
+#define MCF_INTC0_ICR59 (*(vuint8 *)(0x40000C7B))
+#define MCF_INTC0_ICR60 (*(vuint8 *)(0x40000C7C))
+#define MCF_INTC0_ICR61 (*(vuint8 *)(0x40000C7D))
+#define MCF_INTC0_ICR62 (*(vuint8 *)(0x40000C7E))
+#define MCF_INTC0_ICR63 (*(vuint8 *)(0x40000C7F))
+#define MCF_INTC0_SWIACK (*(vuint8 *)(0x40000CE0))
+#define MCF_INTC0_L1IACK (*(vuint8 *)(0x40000CE4))
+#define MCF_INTC0_L2IACK (*(vuint8 *)(0x40000CE8))
+#define MCF_INTC0_L3IACK (*(vuint8 *)(0x40000CEC))
+#define MCF_INTC0_L4IACK (*(vuint8 *)(0x40000CF0))
+#define MCF_INTC0_L5IACK (*(vuint8 *)(0x40000CF4))
+#define MCF_INTC0_L6IACK (*(vuint8 *)(0x40000CF8))
+#define MCF_INTC0_L7IACK (*(vuint8 *)(0x40000CFC))
+#define MCF_INTC0_ICR(x) (*(vuint8 *)(0x40000C41 + ((x-1)*0x1)))
+#define MCF_INTC0_LIACK(x) (*(vuint8 *)(0x40000CE4 + ((x-1)*0x4)))
+
+#define MCF_INTC1_IPRH (*(vuint32*)(0x40000D00))
+#define MCF_INTC1_IPRL (*(vuint32*)(0x40000D04))
+#define MCF_INTC1_IMRH (*(vuint32*)(0x40000D08))
+#define MCF_INTC1_IMRL (*(vuint32*)(0x40000D0C))
+#define MCF_INTC1_INTFRCH (*(vuint32*)(0x40000D10))
+#define MCF_INTC1_INTFRCL (*(vuint32*)(0x40000D14))
+#define MCF_INTC1_IRLR (*(vuint8 *)(0x40000D18))
+#define MCF_INTC1_IACKLPR (*(vuint8 *)(0x40000D19))
+#define MCF_INTC1_ICR01 (*(vuint8 *)(0x40000D41))
+#define MCF_INTC1_ICR02 (*(vuint8 *)(0x40000D42))
+#define MCF_INTC1_ICR03 (*(vuint8 *)(0x40000D43))
+#define MCF_INTC1_ICR04 (*(vuint8 *)(0x40000D44))
+#define MCF_INTC1_ICR05 (*(vuint8 *)(0x40000D45))
+#define MCF_INTC1_ICR06 (*(vuint8 *)(0x40000D46))
+#define MCF_INTC1_ICR07 (*(vuint8 *)(0x40000D47))
+#define MCF_INTC1_ICR08 (*(vuint8 *)(0x40000D48))
+#define MCF_INTC1_ICR09 (*(vuint8 *)(0x40000D49))
+#define MCF_INTC1_ICR10 (*(vuint8 *)(0x40000D4A))
+#define MCF_INTC1_ICR11 (*(vuint8 *)(0x40000D4B))
+#define MCF_INTC1_ICR12 (*(vuint8 *)(0x40000D4C))
+#define MCF_INTC1_ICR13 (*(vuint8 *)(0x40000D4D))
+#define MCF_INTC1_ICR14 (*(vuint8 *)(0x40000D4E))
+#define MCF_INTC1_ICR15 (*(vuint8 *)(0x40000D4F))
+#define MCF_INTC1_ICR16 (*(vuint8 *)(0x40000D50))
+#define MCF_INTC1_ICR17 (*(vuint8 *)(0x40000D51))
+#define MCF_INTC1_ICR18 (*(vuint8 *)(0x40000D52))
+#define MCF_INTC1_ICR19 (*(vuint8 *)(0x40000D53))
+#define MCF_INTC1_ICR20 (*(vuint8 *)(0x40000D54))
+#define MCF_INTC1_ICR21 (*(vuint8 *)(0x40000D55))
+#define MCF_INTC1_ICR22 (*(vuint8 *)(0x40000D56))
+#define MCF_INTC1_ICR23 (*(vuint8 *)(0x40000D57))
+#define MCF_INTC1_ICR24 (*(vuint8 *)(0x40000D58))
+#define MCF_INTC1_ICR25 (*(vuint8 *)(0x40000D59))
+#define MCF_INTC1_ICR26 (*(vuint8 *)(0x40000D5A))
+#define MCF_INTC1_ICR27 (*(vuint8 *)(0x40000D5B))
+#define MCF_INTC1_ICR28 (*(vuint8 *)(0x40000D5C))
+#define MCF_INTC1_ICR29 (*(vuint8 *)(0x40000D5D))
+#define MCF_INTC1_ICR30 (*(vuint8 *)(0x40000D5E))
+#define MCF_INTC1_ICR31 (*(vuint8 *)(0x40000D5F))
+#define MCF_INTC1_ICR32 (*(vuint8 *)(0x40000D60))
+#define MCF_INTC1_ICR33 (*(vuint8 *)(0x40000D61))
+#define MCF_INTC1_ICR34 (*(vuint8 *)(0x40000D62))
+#define MCF_INTC1_ICR35 (*(vuint8 *)(0x40000D63))
+#define MCF_INTC1_ICR36 (*(vuint8 *)(0x40000D64))
+#define MCF_INTC1_ICR37 (*(vuint8 *)(0x40000D65))
+#define MCF_INTC1_ICR38 (*(vuint8 *)(0x40000D66))
+#define MCF_INTC1_ICR39 (*(vuint8 *)(0x40000D67))
+#define MCF_INTC1_ICR40 (*(vuint8 *)(0x40000D68))
+#define MCF_INTC1_ICR41 (*(vuint8 *)(0x40000D69))
+#define MCF_INTC1_ICR42 (*(vuint8 *)(0x40000D6A))
+#define MCF_INTC1_ICR43 (*(vuint8 *)(0x40000D6B))
+#define MCF_INTC1_ICR44 (*(vuint8 *)(0x40000D6C))
+#define MCF_INTC1_ICR45 (*(vuint8 *)(0x40000D6D))
+#define MCF_INTC1_ICR46 (*(vuint8 *)(0x40000D6E))
+#define MCF_INTC1_ICR47 (*(vuint8 *)(0x40000D6F))
+#define MCF_INTC1_ICR48 (*(vuint8 *)(0x40000D70))
+#define MCF_INTC1_ICR49 (*(vuint8 *)(0x40000D71))
+#define MCF_INTC1_ICR50 (*(vuint8 *)(0x40000D72))
+#define MCF_INTC1_ICR51 (*(vuint8 *)(0x40000D73))
+#define MCF_INTC1_ICR52 (*(vuint8 *)(0x40000D74))
+#define MCF_INTC1_ICR53 (*(vuint8 *)(0x40000D75))
+#define MCF_INTC1_ICR54 (*(vuint8 *)(0x40000D76))
+#define MCF_INTC1_ICR55 (*(vuint8 *)(0x40000D77))
+#define MCF_INTC1_ICR56 (*(vuint8 *)(0x40000D78))
+#define MCF_INTC1_ICR57 (*(vuint8 *)(0x40000D79))
+#define MCF_INTC1_ICR58 (*(vuint8 *)(0x40000D7A))
+#define MCF_INTC1_ICR59 (*(vuint8 *)(0x40000D7B))
+#define MCF_INTC1_ICR60 (*(vuint8 *)(0x40000D7C))
+#define MCF_INTC1_ICR61 (*(vuint8 *)(0x40000D7D))
+#define MCF_INTC1_ICR62 (*(vuint8 *)(0x40000D7E))
+#define MCF_INTC1_ICR63 (*(vuint8 *)(0x40000D7F))
+#define MCF_INTC1_SWIACK (*(vuint8 *)(0x40000DE0))
+#define MCF_INTC1_L1IACK (*(vuint8 *)(0x40000DE4))
+#define MCF_INTC1_L2IACK (*(vuint8 *)(0x40000DE8))
+#define MCF_INTC1_L3IACK (*(vuint8 *)(0x40000DEC))
+#define MCF_INTC1_L4IACK (*(vuint8 *)(0x40000DF0))
+#define MCF_INTC1_L5IACK (*(vuint8 *)(0x40000DF4))
+#define MCF_INTC1_L6IACK (*(vuint8 *)(0x40000DF8))
+#define MCF_INTC1_L7IACK (*(vuint8 *)(0x40000DFC))
+#define MCF_INTC1_ICR(x) (*(vuint8 *)(0x40000D41 + ((x-1)*0x1)))
+#define MCF_INTC1_LIACK(x) (*(vuint8 *)(0x40000DE4 + ((x-1)*0x4)))
+
+#define MCF_INTC_IPRH(x) (*(vuint32*)(0x40000C00 + ((x)*0x100)))
+#define MCF_INTC_IPRL(x) (*(vuint32*)(0x40000C04 + ((x)*0x100)))
+#define MCF_INTC_IMRH(x) (*(vuint32*)(0x40000C08 + ((x)*0x100)))
+#define MCF_INTC_IMRL(x) (*(vuint32*)(0x40000C0C + ((x)*0x100)))
+#define MCF_INTC_INTFRCH(x) (*(vuint32*)(0x40000C10 + ((x)*0x100)))
+#define MCF_INTC_INTFRCL(x) (*(vuint32*)(0x40000C14 + ((x)*0x100)))
+#define MCF_INTC_IRLR(x) (*(vuint8 *)(0x40000C18 + ((x)*0x100)))
+#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(0x40000C19 + ((x)*0x100)))
+#define MCF_INTC_ICR01(x) (*(vuint8 *)(0x40000C41 + ((x)*0x100)))
+#define MCF_INTC_ICR02(x) (*(vuint8 *)(0x40000C42 + ((x)*0x100)))
+#define MCF_INTC_ICR03(x) (*(vuint8 *)(0x40000C43 + ((x)*0x100)))
+#define MCF_INTC_ICR04(x) (*(vuint8 *)(0x40000C44 + ((x)*0x100)))
+#define MCF_INTC_ICR05(x) (*(vuint8 *)(0x40000C45 + ((x)*0x100)))
+#define MCF_INTC_ICR06(x) (*(vuint8 *)(0x40000C46 + ((x)*0x100)))
+#define MCF_INTC_ICR07(x) (*(vuint8 *)(0x40000C47 + ((x)*0x100)))
+#define MCF_INTC_ICR08(x) (*(vuint8 *)(0x40000C48 + ((x)*0x100)))
+#define MCF_INTC_ICR09(x) (*(vuint8 *)(0x40000C49 + ((x)*0x100)))
+#define MCF_INTC_ICR10(x) (*(vuint8 *)(0x40000C4A + ((x)*0x100)))
+#define MCF_INTC_ICR11(x) (*(vuint8 *)(0x40000C4B + ((x)*0x100)))
+#define MCF_INTC_ICR12(x) (*(vuint8 *)(0x40000C4C + ((x)*0x100)))
+#define MCF_INTC_ICR13(x) (*(vuint8 *)(0x40000C4D + ((x)*0x100)))
+#define MCF_INTC_ICR14(x) (*(vuint8 *)(0x40000C4E + ((x)*0x100)))
+#define MCF_INTC_ICR15(x) (*(vuint8 *)(0x40000C4F + ((x)*0x100)))
+#define MCF_INTC_ICR16(x) (*(vuint8 *)(0x40000C50 + ((x)*0x100)))
+#define MCF_INTC_ICR17(x) (*(vuint8 *)(0x40000C51 + ((x)*0x100)))
+#define MCF_INTC_ICR18(x) (*(vuint8 *)(0x40000C52 + ((x)*0x100)))
+#define MCF_INTC_ICR19(x) (*(vuint8 *)(0x40000C53 + ((x)*0x100)))
+#define MCF_INTC_ICR20(x) (*(vuint8 *)(0x40000C54 + ((x)*0x100)))
+#define MCF_INTC_ICR21(x) (*(vuint8 *)(0x40000C55 + ((x)*0x100)))
+#define MCF_INTC_ICR22(x) (*(vuint8 *)(0x40000C56 + ((x)*0x100)))
+#define MCF_INTC_ICR23(x) (*(vuint8 *)(0x40000C57 + ((x)*0x100)))
+#define MCF_INTC_ICR24(x) (*(vuint8 *)(0x40000C58 + ((x)*0x100)))
+#define MCF_INTC_ICR25(x) (*(vuint8 *)(0x40000C59 + ((x)*0x100)))
+#define MCF_INTC_ICR26(x) (*(vuint8 *)(0x40000C5A + ((x)*0x100)))
+#define MCF_INTC_ICR27(x) (*(vuint8 *)(0x40000C5B + ((x)*0x100)))
+#define MCF_INTC_ICR28(x) (*(vuint8 *)(0x40000C5C + ((x)*0x100)))
+#define MCF_INTC_ICR29(x) (*(vuint8 *)(0x40000C5D + ((x)*0x100)))
+#define MCF_INTC_ICR30(x) (*(vuint8 *)(0x40000C5E + ((x)*0x100)))
+#define MCF_INTC_ICR31(x) (*(vuint8 *)(0x40000C5F + ((x)*0x100)))
+#define MCF_INTC_ICR32(x) (*(vuint8 *)(0x40000C60 + ((x)*0x100)))
+#define MCF_INTC_ICR33(x) (*(vuint8 *)(0x40000C61 + ((x)*0x100)))
+#define MCF_INTC_ICR34(x) (*(vuint8 *)(0x40000C62 + ((x)*0x100)))
+#define MCF_INTC_ICR35(x) (*(vuint8 *)(0x40000C63 + ((x)*0x100)))
+#define MCF_INTC_ICR36(x) (*(vuint8 *)(0x40000C64 + ((x)*0x100)))
+#define MCF_INTC_ICR37(x) (*(vuint8 *)(0x40000C65 + ((x)*0x100)))
+#define MCF_INTC_ICR38(x) (*(vuint8 *)(0x40000C66 + ((x)*0x100)))
+#define MCF_INTC_ICR39(x) (*(vuint8 *)(0x40000C67 + ((x)*0x100)))
+#define MCF_INTC_ICR40(x) (*(vuint8 *)(0x40000C68 + ((x)*0x100)))
+#define MCF_INTC_ICR41(x) (*(vuint8 *)(0x40000C69 + ((x)*0x100)))
+#define MCF_INTC_ICR42(x) (*(vuint8 *)(0x40000C6A + ((x)*0x100)))
+#define MCF_INTC_ICR43(x) (*(vuint8 *)(0x40000C6B + ((x)*0x100)))
+#define MCF_INTC_ICR44(x) (*(vuint8 *)(0x40000C6C + ((x)*0x100)))
+#define MCF_INTC_ICR45(x) (*(vuint8 *)(0x40000C6D + ((x)*0x100)))
+#define MCF_INTC_ICR46(x) (*(vuint8 *)(0x40000C6E + ((x)*0x100)))
+#define MCF_INTC_ICR47(x) (*(vuint8 *)(0x40000C6F + ((x)*0x100)))
+#define MCF_INTC_ICR48(x) (*(vuint8 *)(0x40000C70 + ((x)*0x100)))
+#define MCF_INTC_ICR49(x) (*(vuint8 *)(0x40000C71 + ((x)*0x100)))
+#define MCF_INTC_ICR50(x) (*(vuint8 *)(0x40000C72 + ((x)*0x100)))
+#define MCF_INTC_ICR51(x) (*(vuint8 *)(0x40000C73 + ((x)*0x100)))
+#define MCF_INTC_ICR52(x) (*(vuint8 *)(0x40000C74 + ((x)*0x100)))
+#define MCF_INTC_ICR53(x) (*(vuint8 *)(0x40000C75 + ((x)*0x100)))
+#define MCF_INTC_ICR54(x) (*(vuint8 *)(0x40000C76 + ((x)*0x100)))
+#define MCF_INTC_ICR55(x) (*(vuint8 *)(0x40000C77 + ((x)*0x100)))
+#define MCF_INTC_ICR56(x) (*(vuint8 *)(0x40000C78 + ((x)*0x100)))
+#define MCF_INTC_ICR57(x) (*(vuint8 *)(0x40000C79 + ((x)*0x100)))
+#define MCF_INTC_ICR58(x) (*(vuint8 *)(0x40000C7A + ((x)*0x100)))
+#define MCF_INTC_ICR59(x) (*(vuint8 *)(0x40000C7B + ((x)*0x100)))
+#define MCF_INTC_ICR60(x) (*(vuint8 *)(0x40000C7C + ((x)*0x100)))
+#define MCF_INTC_ICR61(x) (*(vuint8 *)(0x40000C7D + ((x)*0x100)))
+#define MCF_INTC_ICR62(x) (*(vuint8 *)(0x40000C7E + ((x)*0x100)))
+#define MCF_INTC_ICR63(x) (*(vuint8 *)(0x40000C7F + ((x)*0x100)))
+#define MCF_INTC_SWIACK(x) (*(vuint8 *)(0x40000CE0 + ((x)*0x100)))
+#define MCF_INTC_L1IACK(x) (*(vuint8 *)(0x40000CE4 + ((x)*0x100)))
+#define MCF_INTC_L2IACK(x) (*(vuint8 *)(0x40000CE8 + ((x)*0x100)))
+#define MCF_INTC_L3IACK(x) (*(vuint8 *)(0x40000CEC + ((x)*0x100)))
+#define MCF_INTC_L4IACK(x) (*(vuint8 *)(0x40000CF0 + ((x)*0x100)))
+#define MCF_INTC_L5IACK(x) (*(vuint8 *)(0x40000CF4 + ((x)*0x100)))
+#define MCF_INTC_L6IACK(x) (*(vuint8 *)(0x40000CF8 + ((x)*0x100)))
+#define MCF_INTC_L7IACK(x) (*(vuint8 *)(0x40000CFC + ((x)*0x100)))
+
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32 (0x1)
+#define MCF_INTC_IPRH_INT33 (0x2)
+#define MCF_INTC_IPRH_INT34 (0x4)
+#define MCF_INTC_IPRH_INT35 (0x8)
+#define MCF_INTC_IPRH_INT36 (0x10)
+#define MCF_INTC_IPRH_INT37 (0x20)
+#define MCF_INTC_IPRH_INT38 (0x40)
+#define MCF_INTC_IPRH_INT39 (0x80)
+#define MCF_INTC_IPRH_INT40 (0x100)
+#define MCF_INTC_IPRH_INT41 (0x200)
+#define MCF_INTC_IPRH_INT42 (0x400)
+#define MCF_INTC_IPRH_INT43 (0x800)
+#define MCF_INTC_IPRH_INT44 (0x1000)
+#define MCF_INTC_IPRH_INT45 (0x2000)
+#define MCF_INTC_IPRH_INT46 (0x4000)
+#define MCF_INTC_IPRH_INT47 (0x8000)
+#define MCF_INTC_IPRH_INT48 (0x10000)
+#define MCF_INTC_IPRH_INT49 (0x20000)
+#define MCF_INTC_IPRH_INT50 (0x40000)
+#define MCF_INTC_IPRH_INT51 (0x80000)
+#define MCF_INTC_IPRH_INT52 (0x100000)
+#define MCF_INTC_IPRH_INT53 (0x200000)
+#define MCF_INTC_IPRH_INT54 (0x400000)
+#define MCF_INTC_IPRH_INT55 (0x800000)
+#define MCF_INTC_IPRH_INT56 (0x1000000)
+#define MCF_INTC_IPRH_INT57 (0x2000000)
+#define MCF_INTC_IPRH_INT58 (0x4000000)
+#define MCF_INTC_IPRH_INT59 (0x8000000)
+#define MCF_INTC_IPRH_INT60 (0x10000000)
+#define MCF_INTC_IPRH_INT61 (0x20000000)
+#define MCF_INTC_IPRH_INT62 (0x40000000)
+#define MCF_INTC_IPRH_INT63 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1 (0x2)
+#define MCF_INTC_IPRL_INT2 (0x4)
+#define MCF_INTC_IPRL_INT3 (0x8)
+#define MCF_INTC_IPRL_INT4 (0x10)
+#define MCF_INTC_IPRL_INT5 (0x20)
+#define MCF_INTC_IPRL_INT6 (0x40)
+#define MCF_INTC_IPRL_INT7 (0x80)
+#define MCF_INTC_IPRL_INT8 (0x100)
+#define MCF_INTC_IPRL_INT9 (0x200)
+#define MCF_INTC_IPRL_INT10 (0x400)
+#define MCF_INTC_IPRL_INT11 (0x800)
+#define MCF_INTC_IPRL_INT12 (0x1000)
+#define MCF_INTC_IPRL_INT13 (0x2000)
+#define MCF_INTC_IPRL_INT14 (0x4000)
+#define MCF_INTC_IPRL_INT15 (0x8000)
+#define MCF_INTC_IPRL_INT16 (0x10000)
+#define MCF_INTC_IPRL_INT17 (0x20000)
+#define MCF_INTC_IPRL_INT18 (0x40000)
+#define MCF_INTC_IPRL_INT19 (0x80000)
+#define MCF_INTC_IPRL_INT20 (0x100000)
+#define MCF_INTC_IPRL_INT21 (0x200000)
+#define MCF_INTC_IPRL_INT22 (0x400000)
+#define MCF_INTC_IPRL_INT23 (0x800000)
+#define MCF_INTC_IPRL_INT24 (0x1000000)
+#define MCF_INTC_IPRL_INT25 (0x2000000)
+#define MCF_INTC_IPRL_INT26 (0x4000000)
+#define MCF_INTC_IPRL_INT27 (0x8000000)
+#define MCF_INTC_IPRL_INT28 (0x10000000)
+#define MCF_INTC_IPRL_INT29 (0x20000000)
+#define MCF_INTC_IPRL_INT30 (0x40000000)
+#define MCF_INTC_IPRL_INT31 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32 (0x1)
+#define MCF_INTC_IMRH_INT_MASK33 (0x2)
+#define MCF_INTC_IMRH_INT_MASK34 (0x4)
+#define MCF_INTC_IMRH_INT_MASK35 (0x8)
+#define MCF_INTC_IMRH_INT_MASK36 (0x10)
+#define MCF_INTC_IMRH_INT_MASK37 (0x20)
+#define MCF_INTC_IMRH_INT_MASK38 (0x40)
+#define MCF_INTC_IMRH_INT_MASK39 (0x80)
+#define MCF_INTC_IMRH_INT_MASK40 (0x100)
+#define MCF_INTC_IMRH_INT_MASK41 (0x200)
+#define MCF_INTC_IMRH_INT_MASK42 (0x400)
+#define MCF_INTC_IMRH_INT_MASK43 (0x800)
+#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
+#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
+#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
+#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
+#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
+#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
+#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
+#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
+#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
+#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
+#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
+#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
+#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
+#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
+#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
+#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
+#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL (0x1)
+#define MCF_INTC_IMRL_INT_MASK1 (0x2)
+#define MCF_INTC_IMRL_INT_MASK2 (0x4)
+#define MCF_INTC_IMRL_INT_MASK3 (0x8)
+#define MCF_INTC_IMRL_INT_MASK4 (0x10)
+#define MCF_INTC_IMRL_INT_MASK5 (0x20)
+#define MCF_INTC_IMRL_INT_MASK6 (0x40)
+#define MCF_INTC_IMRL_INT_MASK7 (0x80)
+#define MCF_INTC_IMRL_INT_MASK8 (0x100)
+#define MCF_INTC_IMRL_INT_MASK9 (0x200)
+#define MCF_INTC_IMRL_INT_MASK10 (0x400)
+#define MCF_INTC_IMRL_INT_MASK11 (0x800)
+#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
+#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
+#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
+#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
+#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
+#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
+#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
+#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
+#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
+#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
+#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
+#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
+#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
+#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
+#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
+#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
+#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
+#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
+#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
+#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
+#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
+#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
+#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
+#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
+#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
+#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
+#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
+#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
+#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
+#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
+#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
+#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
+#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
+#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
+#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
+#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
+#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
+#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
+#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
+#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
+#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
+#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
+#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
+#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
+#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
+#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
+#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
+#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
+#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
+#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
+#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
+#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
+#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
+#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
+#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
+#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
+#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
+#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
+#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
+#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
+#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
+#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
+#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
+#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
+#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
+#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
+#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
+#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
+#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
+#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
+#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
+#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_INTC_ICR */
+#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
+#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
+
+/* Bit definitions and macros for MCF_INTC_SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_INTC_LIACK */
+#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
+
+
+#endif /* __MCF52259_INTC_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PAD.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PAD.h new file mode 100644 index 00000000..7c9f1905 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PAD.h @@ -0,0 +1,208 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_PAD_H__
+#define __MCF52259_PAD_H__
+
+
+/*********************************************************************
+*
+* Common GPIO
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PAD_PSRR0 (*(vuint32*)(0x40100078))
+#define MCF_PAD_PDSR0 (*(vuint32*)(0x4010007C))
+#define MCF_PAD_PSRR1 (*(vuint32*)(0x40100080))
+#define MCF_PAD_PSRR2 (*(vuint16*)(0x40100086))
+#define MCF_PAD_PDSR1 (*(vuint32*)(0x40100088))
+#define MCF_PAD_PDSR2 (*(vuint16*)(0x4010008E))
+
+
+/* Bit definitions and macros for MCF_PAD_PSRR0 */
+#define MCF_PAD_PSRR0_PSRR0 (0x1)
+#define MCF_PAD_PSRR0_PSRR1 (0x2)
+#define MCF_PAD_PSRR0_PSRR2 (0x4)
+#define MCF_PAD_PSRR0_PSRR3 (0x8)
+#define MCF_PAD_PSRR0_PSRR4 (0x10)
+#define MCF_PAD_PSRR0_PSRR5 (0x20)
+#define MCF_PAD_PSRR0_PSRR6 (0x40)
+#define MCF_PAD_PSRR0_PSRR7 (0x80)
+#define MCF_PAD_PSRR0_PSRR8 (0x100)
+#define MCF_PAD_PSRR0_PSRR9 (0x200)
+#define MCF_PAD_PSRR0_PSRR10 (0x400)
+#define MCF_PAD_PSRR0_PSRR11 (0x800)
+#define MCF_PAD_PSRR0_PSRR12 (0x1000)
+#define MCF_PAD_PSRR0_PSRR13 (0x2000)
+#define MCF_PAD_PSRR0_PSRR14 (0x4000)
+#define MCF_PAD_PSRR0_PSRR15 (0x8000)
+#define MCF_PAD_PSRR0_PSRR16 (0x10000)
+#define MCF_PAD_PSRR0_PSRR17 (0x20000)
+#define MCF_PAD_PSRR0_PSRR18 (0x40000)
+#define MCF_PAD_PSRR0_PSRR19 (0x80000)
+#define MCF_PAD_PSRR0_PSRR20 (0x100000)
+#define MCF_PAD_PSRR0_PSRR21 (0x200000)
+#define MCF_PAD_PSRR0_PSRR22 (0x400000)
+#define MCF_PAD_PSRR0_PSRR23 (0x800000)
+#define MCF_PAD_PSRR0_PSRR24 (0x1000000)
+#define MCF_PAD_PSRR0_PSRR25 (0x2000000)
+#define MCF_PAD_PSRR0_PSRR26 (0x4000000)
+#define MCF_PAD_PSRR0_PSRR27 (0x8000000)
+#define MCF_PAD_PSRR0_PSRR28 (0x10000000)
+#define MCF_PAD_PSRR0_PSRR29 (0x20000000)
+#define MCF_PAD_PSRR0_PSRR30 (0x40000000)
+#define MCF_PAD_PSRR0_PSRR31 (0x80000000)
+
+/* Bit definitions and macros for MCF_PAD_PDSR0 */
+#define MCF_PAD_PDSR0_PDSR0 (0x1)
+#define MCF_PAD_PDSR0_PDSR1 (0x2)
+#define MCF_PAD_PDSR0_PDSR2 (0x4)
+#define MCF_PAD_PDSR0_PDSR3 (0x8)
+#define MCF_PAD_PDSR0_PDSR4 (0x10)
+#define MCF_PAD_PDSR0_PDSR5 (0x20)
+#define MCF_PAD_PDSR0_PDSR6 (0x40)
+#define MCF_PAD_PDSR0_PDSR7 (0x80)
+#define MCF_PAD_PDSR0_PDSR8 (0x100)
+#define MCF_PAD_PDSR0_PDSR9 (0x200)
+#define MCF_PAD_PDSR0_PDSR10 (0x400)
+#define MCF_PAD_PDSR0_PDSR11 (0x800)
+#define MCF_PAD_PDSR0_PDSR12 (0x1000)
+#define MCF_PAD_PDSR0_PDSR13 (0x2000)
+#define MCF_PAD_PDSR0_PDSR14 (0x4000)
+#define MCF_PAD_PDSR0_PDSR15 (0x8000)
+#define MCF_PAD_PDSR0_PDSR16 (0x10000)
+#define MCF_PAD_PDSR0_PDSR17 (0x20000)
+#define MCF_PAD_PDSR0_PDSR18 (0x40000)
+#define MCF_PAD_PDSR0_PDSR19 (0x80000)
+#define MCF_PAD_PDSR0_PDSR20 (0x100000)
+#define MCF_PAD_PDSR0_PDSR21 (0x200000)
+#define MCF_PAD_PDSR0_PDSR22 (0x400000)
+#define MCF_PAD_PDSR0_PDSR23 (0x800000)
+#define MCF_PAD_PDSR0_PDSR24 (0x1000000)
+#define MCF_PAD_PDSR0_PDSR25 (0x2000000)
+#define MCF_PAD_PDSR0_PDSR26 (0x4000000)
+#define MCF_PAD_PDSR0_PDSR27 (0x8000000)
+#define MCF_PAD_PDSR0_PDSR28 (0x10000000)
+#define MCF_PAD_PDSR0_PDSR29 (0x20000000)
+#define MCF_PAD_PDSR0_PDSR30 (0x40000000)
+#define MCF_PAD_PDSR0_PDSR31 (0x80000000)
+
+/* Bit definitions and macros for MCF_PAD_PSRR1 */
+#define MCF_PAD_PSRR1_PSRR32 (0x1)
+#define MCF_PAD_PSRR1_PSRR33 (0x2)
+#define MCF_PAD_PSRR1_PSRR34 (0x4)
+#define MCF_PAD_PSRR1_PSRR35 (0x8)
+#define MCF_PAD_PSRR1_PSRR36 (0x10)
+#define MCF_PAD_PSRR1_PSRR37 (0x20)
+#define MCF_PAD_PSRR1_PSRR38 (0x40)
+#define MCF_PAD_PSRR1_PSRR39 (0x80)
+#define MCF_PAD_PSRR1_PSRR40 (0x100)
+#define MCF_PAD_PSRR1_PSRR41 (0x200)
+#define MCF_PAD_PSRR1_PSRR42 (0x400)
+#define MCF_PAD_PSRR1_PSRR43 (0x800)
+#define MCF_PAD_PSRR1_PSRR44 (0x1000)
+#define MCF_PAD_PSRR1_PSRR45 (0x2000)
+#define MCF_PAD_PSRR1_PSRR46 (0x4000)
+#define MCF_PAD_PSRR1_PSRR47 (0x8000)
+#define MCF_PAD_PSRR1_PSRR48 (0x10000)
+#define MCF_PAD_PSRR1_PSRR49 (0x20000)
+#define MCF_PAD_PSRR1_PSRR50 (0x40000)
+#define MCF_PAD_PSRR1_PSRR51 (0x80000)
+#define MCF_PAD_PSRR1_PSRR52 (0x100000)
+#define MCF_PAD_PSRR1_PSRR53 (0x200000)
+#define MCF_PAD_PSRR1_PSRR54 (0x400000)
+#define MCF_PAD_PSRR1_PSRR55 (0x800000)
+#define MCF_PAD_PSRR1_PSRR56 (0x1000000)
+#define MCF_PAD_PSRR1_PSRR57 (0x2000000)
+#define MCF_PAD_PSRR1_PSRR58 (0x4000000)
+#define MCF_PAD_PSRR1_PSRR59 (0x8000000)
+#define MCF_PAD_PSRR1_PSRR60 (0x10000000)
+#define MCF_PAD_PSRR1_PSRR61 (0x20000000)
+#define MCF_PAD_PSRR1_PSRR62 (0x40000000)
+#define MCF_PAD_PSRR1_PSRR63 (0x80000000)
+
+/* Bit definitions and macros for MCF_PAD_PSRR2 */
+#define MCF_PAD_PSRR2_PSRR64 (0x1)
+#define MCF_PAD_PSRR2_PSRR65 (0x2)
+#define MCF_PAD_PSRR2_PSRR66 (0x4)
+#define MCF_PAD_PSRR2_PSRR67 (0x8)
+#define MCF_PAD_PSRR2_PSRR68 (0x10)
+#define MCF_PAD_PSRR2_PSRR69 (0x20)
+#define MCF_PAD_PSRR2_PSRR70 (0x40)
+#define MCF_PAD_PSRR2_PSRR71 (0x80)
+#define MCF_PAD_PSRR2_PSRR72 (0x100)
+#define MCF_PAD_PSRR2_PSRR73 (0x200)
+#define MCF_PAD_PSRR2_PSRR74 (0x400)
+#define MCF_PAD_PSRR2_PSRR75 (0x800)
+#define MCF_PAD_PSRR2_PSRR76 (0x1000)
+#define MCF_PAD_PSRR2_PSRR77 (0x2000)
+#define MCF_PAD_PSRR2_PSRR78 (0x4000)
+#define MCF_PAD_PSRR2_PSRR79 (0x8000)
+
+/* Bit definitions and macros for MCF_PAD_PDSR1 */
+#define MCF_PAD_PDSR1_PDSR32 (0x1)
+#define MCF_PAD_PDSR1_PDSR33 (0x2)
+#define MCF_PAD_PDSR1_PDSR34 (0x4)
+#define MCF_PAD_PDSR1_PDSR35 (0x8)
+#define MCF_PAD_PDSR1_PDSR36 (0x10)
+#define MCF_PAD_PDSR1_PDSR37 (0x20)
+#define MCF_PAD_PDSR1_PDSR38 (0x40)
+#define MCF_PAD_PDSR1_PDSR39 (0x80)
+#define MCF_PAD_PDSR1_PDSR40 (0x100)
+#define MCF_PAD_PDSR1_PDSR41 (0x200)
+#define MCF_PAD_PDSR1_PDSR42 (0x400)
+#define MCF_PAD_PDSR1_PDSR43 (0x800)
+#define MCF_PAD_PDSR1_PDSR44 (0x1000)
+#define MCF_PAD_PDSR1_PDSR45 (0x2000)
+#define MCF_PAD_PDSR1_PDSR46 (0x4000)
+#define MCF_PAD_PDSR1_PDSR47 (0x8000)
+#define MCF_PAD_PDSR1_PDSR48 (0x10000)
+#define MCF_PAD_PDSR1_PDSR49 (0x20000)
+#define MCF_PAD_PDSR1_PDSR50 (0x40000)
+#define MCF_PAD_PDSR1_PDSR51 (0x80000)
+#define MCF_PAD_PDSR1_PDSR52 (0x100000)
+#define MCF_PAD_PDSR1_PDSR53 (0x200000)
+#define MCF_PAD_PDSR1_PDSR54 (0x400000)
+#define MCF_PAD_PDSR1_PDSR55 (0x800000)
+#define MCF_PAD_PDSR1_PDSR56 (0x1000000)
+#define MCF_PAD_PDSR1_PDSR57 (0x2000000)
+#define MCF_PAD_PDSR1_PDSR58 (0x4000000)
+#define MCF_PAD_PDSR1_PDSR59 (0x8000000)
+#define MCF_PAD_PDSR1_PDSR60 (0x10000000)
+#define MCF_PAD_PDSR1_PDSR61 (0x20000000)
+#define MCF_PAD_PDSR1_PDSR62 (0x40000000)
+#define MCF_PAD_PDSR1_PDSR63 (0x80000000)
+
+/* Bit definitions and macros for MCF_PAD_PDSR2 */
+#define MCF_PAD_PDSR2_PDSR64 (0x1)
+#define MCF_PAD_PDSR2_PDSR65 (0x2)
+#define MCF_PAD_PDSR2_PDSR66 (0x4)
+#define MCF_PAD_PDSR2_PDSR67 (0x8)
+#define MCF_PAD_PDSR2_PDSR68 (0x10)
+#define MCF_PAD_PDSR2_PDSR69 (0x20)
+#define MCF_PAD_PDSR2_PDSR70 (0x40)
+#define MCF_PAD_PDSR2_PDSR71 (0x80)
+#define MCF_PAD_PDSR2_PDSR72 (0x100)
+#define MCF_PAD_PDSR2_PDSR73 (0x200)
+#define MCF_PAD_PDSR2_PDSR74 (0x400)
+#define MCF_PAD_PDSR2_PDSR75 (0x800)
+#define MCF_PAD_PDSR2_PDSR76 (0x1000)
+#define MCF_PAD_PDSR2_PDSR77 (0x2000)
+#define MCF_PAD_PDSR2_PDSR78 (0x4000)
+#define MCF_PAD_PDSR2_PDSR79 (0x8000)
+
+
+#endif /* __MCF52259_PAD_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PIT.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PIT.h new file mode 100644 index 00000000..16d72184 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PIT.h @@ -0,0 +1,57 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_PIT_H__
+#define __MCF52259_PIT_H__
+
+
+/*********************************************************************
+*
+* Programmable Interrupt Timer (PIT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PIT0_PCSR (*(vuint16*)(0x40150000))
+#define MCF_PIT0_PMR (*(vuint16*)(0x40150002))
+#define MCF_PIT0_PCNTR (*(vuint16*)(0x40150004))
+
+#define MCF_PIT1_PCSR (*(vuint16*)(0x40160000))
+#define MCF_PIT1_PMR (*(vuint16*)(0x40160002))
+#define MCF_PIT1_PCNTR (*(vuint16*)(0x40160004))
+
+#define MCF_PIT_PCSR(x) (*(vuint16*)(0x40150000 + ((x)*0x10000)))
+#define MCF_PIT_PMR(x) (*(vuint16*)(0x40150002 + ((x)*0x10000)))
+#define MCF_PIT_PCNTR(x) (*(vuint16*)(0x40150004 + ((x)*0x10000)))
+
+
+/* Bit definitions and macros for MCF_PIT_PCSR */
+#define MCF_PIT_PCSR_EN (0x1)
+#define MCF_PIT_PCSR_RLD (0x2)
+#define MCF_PIT_PCSR_PIF (0x4)
+#define MCF_PIT_PCSR_PIE (0x8)
+#define MCF_PIT_PCSR_OVW (0x10)
+#define MCF_PIT_PCSR_DBG (0x20)
+#define MCF_PIT_PCSR_DOZE (0x40)
+#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)
+
+/* Bit definitions and macros for MCF_PIT_PMR */
+#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PIT_PCNTR */
+#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF52259_PIT_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PMM.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PMM.h new file mode 100644 index 00000000..a24efd8e --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PMM.h @@ -0,0 +1,49 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_PMM_H__
+#define __MCF52259_PMM_H__
+
+
+/*********************************************************************
+*
+* Power Management (PMM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PMM_LPICR (*(vuint8 *)(0x40000012))
+#define MCF_PMM_LPCR (*(vuint8 *)(0x40110007))
+
+
+/* Bit definitions and macros for MCF_PMM_LPICR */
+#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)
+#define MCF_PMM_LPICR_ENBSTOP (0x80)
+
+/* Bit definitions and macros for MCF_PMM_LPCR */
+#define MCF_PMM_LPCR_LVDSE (0x2)
+#define MCF_PMM_LPCR_STPMD(x) (((x)&0x3)<<0x3)
+#define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0)
+#define MCF_PMM_LPCR_STPMD_SYS_CLKOUT_DISABLED (0x8)
+#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x10)
+#define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x18)
+#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)
+#define MCF_PMM_LPCR_LPMD_RUN (0)
+#define MCF_PMM_LPCR_LPMD_DOZE (0x40)
+#define MCF_PMM_LPCR_LPMD_WAIT (0x80)
+#define MCF_PMM_LPCR_LPMD_STOP (0xC0)
+
+
+#endif /* __MCF52259_PMM_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PWM.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PWM.h new file mode 100644 index 00000000..8cadac20 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_PWM.h @@ -0,0 +1,142 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_PWM_H__
+#define __MCF52259_PWM_H__
+
+
+/*********************************************************************
+*
+* Pulse Width Modulation (PWM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PWM_PWME (*(vuint8 *)(0x401B0000))
+#define MCF_PWM_PWMPOL (*(vuint8 *)(0x401B0001))
+#define MCF_PWM_PWMCLK (*(vuint8 *)(0x401B0002))
+#define MCF_PWM_PWMPRCLK (*(vuint8 *)(0x401B0003))
+#define MCF_PWM_PWMCAE (*(vuint8 *)(0x401B0004))
+#define MCF_PWM_PWMCTL (*(vuint8 *)(0x401B0005))
+#define MCF_PWM_PWMSCLA (*(vuint8 *)(0x401B0008))
+#define MCF_PWM_PWMSCLB (*(vuint8 *)(0x401B0009))
+#define MCF_PWM_PWMCNT0 (*(vuint8 *)(0x401B000C))
+#define MCF_PWM_PWMCNT1 (*(vuint8 *)(0x401B000D))
+#define MCF_PWM_PWMCNT2 (*(vuint8 *)(0x401B000E))
+#define MCF_PWM_PWMCNT3 (*(vuint8 *)(0x401B000F))
+#define MCF_PWM_PWMCNT4 (*(vuint8 *)(0x401B0010))
+#define MCF_PWM_PWMCNT5 (*(vuint8 *)(0x401B0011))
+#define MCF_PWM_PWMCNT6 (*(vuint8 *)(0x401B0012))
+#define MCF_PWM_PWMCNT7 (*(vuint8 *)(0x401B0013))
+#define MCF_PWM_PWMPER0 (*(vuint8 *)(0x401B0014))
+#define MCF_PWM_PWMPER1 (*(vuint8 *)(0x401B0015))
+#define MCF_PWM_PWMPER2 (*(vuint8 *)(0x401B0016))
+#define MCF_PWM_PWMPER3 (*(vuint8 *)(0x401B0017))
+#define MCF_PWM_PWMPER4 (*(vuint8 *)(0x401B0018))
+#define MCF_PWM_PWMPER5 (*(vuint8 *)(0x401B0019))
+#define MCF_PWM_PWMPER6 (*(vuint8 *)(0x401B001A))
+#define MCF_PWM_PWMPER7 (*(vuint8 *)(0x401B001B))
+#define MCF_PWM_PWMDTY0 (*(vuint8 *)(0x401B001C))
+#define MCF_PWM_PWMDTY1 (*(vuint8 *)(0x401B001D))
+#define MCF_PWM_PWMDTY2 (*(vuint8 *)(0x401B001E))
+#define MCF_PWM_PWMDTY3 (*(vuint8 *)(0x401B001F))
+#define MCF_PWM_PWMDTY4 (*(vuint8 *)(0x401B0020))
+#define MCF_PWM_PWMDTY5 (*(vuint8 *)(0x401B0021))
+#define MCF_PWM_PWMDTY6 (*(vuint8 *)(0x401B0022))
+#define MCF_PWM_PWMDTY7 (*(vuint8 *)(0x401B0023))
+#define MCF_PWM_PWMSDN (*(vuint8 *)(0x401B0024))
+#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0x401B000C + ((x)*0x1)))
+#define MCF_PWM_PWMPER(x) (*(vuint8 *)(0x401B0014 + ((x)*0x1)))
+#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0x401B001C + ((x)*0x1)))
+
+
+/* Bit definitions and macros for MCF_PWM_PWME */
+#define MCF_PWM_PWME_PWME0 (0x1)
+#define MCF_PWM_PWME_PWME1 (0x2)
+#define MCF_PWM_PWME_PWME2 (0x4)
+#define MCF_PWM_PWME_PWME3 (0x8)
+#define MCF_PWM_PWME_PWME4 (0x10)
+#define MCF_PWM_PWME_PWME5 (0x20)
+#define MCF_PWM_PWME_PWME6 (0x40)
+#define MCF_PWM_PWME_PWME7 (0x80)
+
+/* Bit definitions and macros for MCF_PWM_PWMPOL */
+#define MCF_PWM_PWMPOL_PPOL0 (0x1)
+#define MCF_PWM_PWMPOL_PPOL1 (0x2)
+#define MCF_PWM_PWMPOL_PPOL2 (0x4)
+#define MCF_PWM_PWMPOL_PPOL3 (0x8)
+#define MCF_PWM_PWMPOL_PPOL4 (0x10)
+#define MCF_PWM_PWMPOL_PPOL5 (0x20)
+#define MCF_PWM_PWMPOL_PPOL6 (0x40)
+#define MCF_PWM_PWMPOL_PPOL7 (0x80)
+
+/* Bit definitions and macros for MCF_PWM_PWMCLK */
+#define MCF_PWM_PWMCLK_PCLK0 (0x1)
+#define MCF_PWM_PWMCLK_PCLK1 (0x2)
+#define MCF_PWM_PWMCLK_PCLK2 (0x4)
+#define MCF_PWM_PWMCLK_PCLK3 (0x8)
+#define MCF_PWM_PWMCLK_PCLK4 (0x10)
+#define MCF_PWM_PWMCLK_PCLK5 (0x20)
+#define MCF_PWM_PWMCLK_PCLK6 (0x40)
+#define MCF_PWM_PWMCLK_PCLK7 (0x80)
+
+/* Bit definitions and macros for MCF_PWM_PWMPRCLK */
+#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x7)<<0)
+#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_PWM_PWMCAE */
+#define MCF_PWM_PWMCAE_CAE0 (0x1)
+#define MCF_PWM_PWMCAE_CAE1 (0x2)
+#define MCF_PWM_PWMCAE_CAE2 (0x4)
+#define MCF_PWM_PWMCAE_CAE3 (0x8)
+#define MCF_PWM_PWMCAE_CAE4 (0x10)
+#define MCF_PWM_PWMCAE_CAE5 (0x20)
+#define MCF_PWM_PWMCAE_CAE6 (0x40)
+#define MCF_PWM_PWMCAE_CAE7 (0x80)
+
+/* Bit definitions and macros for MCF_PWM_PWMCTL */
+#define MCF_PWM_PWMCTL_PFRZ (0x4)
+#define MCF_PWM_PWMCTL_PSWAI (0x8)
+#define MCF_PWM_PWMCTL_CON01 (0x10)
+#define MCF_PWM_PWMCTL_CON23 (0x20)
+#define MCF_PWM_PWMCTL_CON45 (0x40)
+#define MCF_PWM_PWMCTL_CON67 (0x80)
+
+/* Bit definitions and macros for MCF_PWM_PWMSCLA */
+#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PWM_PWMSCLB */
+#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PWM_PWMCNT */
+#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PWM_PWMPER */
+#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PWM_PWMDTY */
+#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PWM_PWMSDN */
+#define MCF_PWM_PWMSDN_SDNEN (0x1)
+#define MCF_PWM_PWMSDN_PWM7IL (0x2)
+#define MCF_PWM_PWMSDN_PWM7IN (0x4)
+#define MCF_PWM_PWMSDN_LVL (0x10)
+#define MCF_PWM_PWMSDN_RESTART (0x20)
+#define MCF_PWM_PWMSDN_IE (0x40)
+#define MCF_PWM_PWMSDN_IF (0x80)
+
+
+#endif /* __MCF52259_PWM_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_QSPI.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_QSPI.h new file mode 100644 index 00000000..37602971 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_QSPI.h @@ -0,0 +1,86 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_QSPI_H__
+#define __MCF52259_QSPI_H__
+
+
+/*********************************************************************
+*
+* Queued Serial Peripheral Interface (QSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_QSPI_QMR (*(vuint16*)(0x40000340))
+#define MCF_QSPI_QDLYR (*(vuint16*)(0x40000344))
+#define MCF_QSPI_QWR (*(vuint16*)(0x40000348))
+#define MCF_QSPI_QIR (*(vuint16*)(0x4000034C))
+#define MCF_QSPI_QAR (*(vuint16*)(0x40000350))
+#define MCF_QSPI_QDR (*(vuint16*)(0x40000354))
+
+
+/* Bit definitions and macros for MCF_QSPI_QMR */
+#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)
+#define MCF_QSPI_QMR_CPHA (0x100)
+#define MCF_QSPI_QMR_CPOL (0x200)
+#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)
+#define MCF_QSPI_QMR_DOHIE (0x4000)
+#define MCF_QSPI_QMR_MSTR (0x8000)
+
+/* Bit definitions and macros for MCF_QSPI_QDLYR */
+#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)
+#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)
+#define MCF_QSPI_QDLYR_SPE (0x8000)
+
+/* Bit definitions and macros for MCF_QSPI_QWR */
+#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)
+#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)
+#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)
+#define MCF_QSPI_QWR_CSIV (0x1000)
+#define MCF_QSPI_QWR_WRTO (0x2000)
+#define MCF_QSPI_QWR_WREN (0x4000)
+#define MCF_QSPI_QWR_HALT (0x8000)
+
+/* Bit definitions and macros for MCF_QSPI_QIR */
+#define MCF_QSPI_QIR_SPIF (0x1)
+#define MCF_QSPI_QIR_ABRT (0x4)
+#define MCF_QSPI_QIR_WCEF (0x8)
+#define MCF_QSPI_QIR_SPIFE (0x100)
+#define MCF_QSPI_QIR_ABRTE (0x400)
+#define MCF_QSPI_QIR_WCEFE (0x800)
+#define MCF_QSPI_QIR_ABRTL (0x1000)
+#define MCF_QSPI_QIR_ABRTB (0x4000)
+#define MCF_QSPI_QIR_WCEFB (0x8000)
+
+/* Bit definitions and macros for MCF_QSPI_QAR */
+#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)
+#define MCF_QSPI_QAR_TRANS (0)
+#define MCF_QSPI_QAR_RECV (0x10)
+#define MCF_QSPI_QAR_CMD (0x20)
+
+/* Bit definitions and macros for MCF_QSPI_QDR */
+#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)
+#define MCF_QSPI_QDR_CONT (0x8000)
+#define MCF_QSPI_QDR_BITSE (0x4000)
+#define MCF_QSPI_QDR_DT (0x2000)
+#define MCF_QSPI_QDR_DSCK (0x1000)
+#define MCF_QSPI_QDR_QSPI_CS3 (0x800)
+#define MCF_QSPI_QDR_QSPI_CS2 (0x400)
+#define MCF_QSPI_QDR_QSPI_CS1 (0x200)
+#define MCF_QSPI_QDR_QSPI_CS0 (0x100)
+
+
+#endif /* __MCF52259_QSPI_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_RCM.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_RCM.h new file mode 100644 index 00000000..eba4cf93 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_RCM.h @@ -0,0 +1,49 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_RCM_H__
+#define __MCF52259_RCM_H__
+
+
+/*********************************************************************
+*
+* Reset Controller Module (RCM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_RCM_RCR (*(vuint8 *)(0x40110000))
+#define MCF_RCM_RSR (*(vuint8 *)(0x40110001))
+
+
+/* Bit definitions and macros for MCF_RCM_RCR */
+#define MCF_RCM_RCR_LVDE (0x1)
+#define MCF_RCM_RCR_LVDRE (0x4)
+#define MCF_RCM_RCR_LVDIE (0x8)
+#define MCF_RCM_RCR_LVDF (0x10)
+#define MCF_RCM_RCR_FRCRSTOUT (0x40)
+#define MCF_RCM_RCR_SOFTRST (0x80)
+
+/* Bit definitions and macros for MCF_RCM_RSR */
+#define MCF_RCM_RSR_LOL (0x1)
+#define MCF_RCM_RSR_LOC (0x2)
+#define MCF_RCM_RSR_EXT (0x4)
+#define MCF_RCM_RSR_POR (0x8)
+#define MCF_RCM_RSR_WDR (0x10)
+#define MCF_RCM_RSR_SOFT (0x20)
+#define MCF_RCM_RSR_LVD (0x40)
+
+
+#endif /* __MCF52259_RCM_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_RNGA.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_RNGA.h new file mode 100644 index 00000000..232abcdc --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_RNGA.h @@ -0,0 +1,56 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_RNGA_H__
+#define __MCF52259_RNGA_H__
+
+
+/*********************************************************************
+*
+* Random Number Generator (RNG)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_RNGA_RNGCR (*(vuint32*)(0x401F0000))
+#define MCF_RNGA_RNGSR (*(vuint32*)(0x401F0004))
+#define MCF_RNGA_RNGER (*(vuint32*)(0x401F0008))
+#define MCF_RNGA_RNGOUT (*(vuint32*)(0x401F000C))
+
+
+/* Bit definitions and macros for MCF_RNGA_RNGCR */
+#define MCF_RNGA_RNGCR_GO (0x1)
+#define MCF_RNGA_RNGCR_HA (0x2)
+#define MCF_RNGA_RNGCR_IM (0x4)
+#define MCF_RNGA_RNGCR_CI (0x8)
+#define MCF_RNGA_RNGCR_SLM (0x10)
+
+/* Bit definitions and macros for MCF_RNGA_RNGSR */
+#define MCF_RNGA_RNGSR_SV (0x1)
+#define MCF_RNGA_RNGSR_LRS (0x2)
+#define MCF_RNGA_RNGSR_FUF (0x4)
+#define MCF_RNGA_RNGSR_EI (0x8)
+#define MCF_RNGA_RNGSR_SLP (0x10)
+#define MCF_RNGA_RNGSR_OFL(x) (((x)&0xFF)<<0x8)
+#define MCF_RNGA_RNGSR_OFS(x) (((x)&0xFF)<<0x10)
+
+/* Bit definitions and macros for MCF_RNGA_RNGER */
+#define MCF_RNGA_RNGER_ENT(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_RNGA_RNGOUT */
+#define MCF_RNGA_RNGOUT_RANDOM_OUTPUT(x) (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF52259_RNGA_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_RTC.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_RTC.h new file mode 100644 index 00000000..9559d438 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_RTC.h @@ -0,0 +1,91 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_RTC_H__
+#define __MCF52259_RTC_H__
+
+
+/*********************************************************************
+*
+* Real-Time Clock (RTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_RTC_HOURMIN (*(vuint32*)(0x40180000))
+#define MCF_RTC_SECONDS (*(vuint32*)(0x40180004))
+#define MCF_RTC_ALRM_HM (*(vuint32*)(0x40180008))
+#define MCF_RTC_ALRM_SEC (*(vuint32*)(0x4018000C))
+#define MCF_RTC_RTCCTL (*(vuint32*)(0x40180010))
+#define MCF_RTC_RTCISR (*(vuint32*)(0x40180014))
+#define MCF_RTC_RTCIENR (*(vuint32*)(0x40180018))
+#define MCF_RTC_STPWCH (*(vuint32*)(0x4018001C))
+#define MCF_RTC_DAYS (*(vuint32*)(0x40180020))
+#define MCF_RTC_ALRM_DAY (*(vuint32*)(0x40180024))
+#define MCF_RTC_RTCGOCU (*(vuint32*)(0x40180034))
+#define MCF_RTC_RTCGOCL (*(vuint32*)(0x40180038))
+
+
+/* Bit definitions and macros for MCF_RTC_HOURMIN */
+#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x3F)<<0)
+#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x1F)<<0x8)
+
+/* Bit definitions and macros for MCF_RTC_SECONDS */
+#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_RTC_ALRM_HM */
+#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x3F)<<0)
+#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x1F)<<0x8)
+
+/* Bit definitions and macros for MCF_RTC_ALRM_SEC */
+#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_RTC_RTCCTL */
+#define MCF_RTC_RTCCTL_SWR (0x1)
+#define MCF_RTC_RTCCTL_EN (0x80)
+
+/* Bit definitions and macros for MCF_RTC_RTCISR */
+#define MCF_RTC_RTCISR_SW (0x1)
+#define MCF_RTC_RTCISR_MIN (0x2)
+#define MCF_RTC_RTCISR_ALM (0x4)
+#define MCF_RTC_RTCISR_DAY (0x8)
+#define MCF_RTC_RTCISR_1HZ (0x10)
+#define MCF_RTC_RTCISR_HR (0x20)
+
+/* Bit definitions and macros for MCF_RTC_RTCIENR */
+#define MCF_RTC_RTCIENR_SW (0x1)
+#define MCF_RTC_RTCIENR_MIN (0x2)
+#define MCF_RTC_RTCIENR_ALM (0x4)
+#define MCF_RTC_RTCIENR_DAY (0x8)
+#define MCF_RTC_RTCIENR_1HZ (0x10)
+#define MCF_RTC_RTCIENR_HR (0x20)
+
+/* Bit definitions and macros for MCF_RTC_STPWCH */
+#define MCF_RTC_STPWCH_CNT(x) (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_RTC_DAYS */
+#define MCF_RTC_DAYS_DAYS(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_RTC_ALRM_DAY */
+#define MCF_RTC_ALRM_DAY_DAYSAL(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_RTC_RTCGOCU */
+#define MCF_RTC_RTCGOCU_RTCGOCNT(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_RTC_RTCGOCL */
+#define MCF_RTC_RTCGOCL_RTCGOCNT(x) (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF52259_RTC_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_SCM.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_SCM.h new file mode 100644 index 00000000..08cac2ec --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_SCM.h @@ -0,0 +1,215 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_SCM_H__
+#define __MCF52259_SCM_H__
+
+
+/*********************************************************************
+*
+* System Control Module (SCM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x8]))
+#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0xC]))
+#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x10]))
+#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x11]))
+#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x13]))
+#define MCF_SCM_DMAREQC (*(vuint32*)(&__IPSBAR[0x14]))
+#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x18]))
+#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x1C]))
+#define MCF_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x20]))
+#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x21]))
+#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x22]))
+#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x23]))
+#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x24]))
+#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x25]))
+#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x26]))
+#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x27]))
+#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x28]))
+#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x29]))
+#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x2A]))
+#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x2B]))
+#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x2C]))
+#define MCF_SCM_PACR10 (*(vuint8 *)(&__IPSBAR[0x2E]))
+#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x30]))
+#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x31]))
+#define MCF_SCM_PACR(x) (*(vuint8 *)(&__IPSBAR[0x24 + ((x)*0x1)]))
+#define MCF_SCM_GPACR(x) (*(vuint8 *)(&__IPSBAR[0x30 + ((x)*0x1)]))
+
+/* Other macros */
+#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x0]))
+#define MCF_SCM_IPSBAR_V (0x1)
+#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)
+
+
+/* Bit definitions and macros for MCF_SCM_RAMBAR */
+#define MCF_SCM_RAMBAR_BDE (0x200)
+#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_SCM_PPMRH */
+#define MCF_SCM_PPMRH_CDGPIO (0x1)
+#define MCF_SCM_PPMRH_CDEPORT (0x2)
+#define MCF_SCM_PPMRH_CDPIT0 (0x8)
+#define MCF_SCM_PPMRH_CDPIT1 (0x10)
+#define MCF_SCM_PPMRH_CDADC (0x80)
+#define MCF_SCM_PPMRH_CDGPT (0x100)
+#define MCF_SCM_PPMRH_CDPWM (0x200)
+#define MCF_SCM_PPMRH_CDCFM (0x800)
+#define MCF_SCM_PPMRH_CDUSB (0x1000)
+
+/* Bit definitions and macros for MCF_SCM_CRSR */
+#define MCF_SCM_CRSR_EXT (0x80)
+
+/* Bit definitions and macros for MCF_SCM_CWCR */
+#define MCF_SCM_CWCR_CWTIF (0x1)
+#define MCF_SCM_CWCR_CWTAVAL (0x2)
+#define MCF_SCM_CWCR_CWTA (0x4)
+#define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)
+#define MCF_SCM_CWCR_CWT_2_9 (0)
+#define MCF_SCM_CWCR_CWT_2_11 (0x8)
+#define MCF_SCM_CWCR_CWT_2_13 (0x10)
+#define MCF_SCM_CWCR_CWT_2_15 (0x18)
+#define MCF_SCM_CWCR_CWT_2_19 (0x20)
+#define MCF_SCM_CWCR_CWT_2_23 (0x28)
+#define MCF_SCM_CWCR_CWT_2_27 (0x30)
+#define MCF_SCM_CWCR_CWT_2_31 (0x38)
+#define MCF_SCM_CWCR_CWRI (0x40)
+#define MCF_SCM_CWCR_CWE (0x80)
+
+/* Bit definitions and macros for MCF_SCM_CWSR */
+#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_SCM_DMAREQC */
+#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)
+#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)
+#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)
+#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)
+
+/* Bit definitions and macros for MCF_SCM_PPMRL */
+#define MCF_SCM_PPMRL_CDG (0x2)
+#define MCF_SCM_PPMRL_CDMINIBUS (0x8)
+#define MCF_SCM_PPMRL_CDDMA (0x10)
+#define MCF_SCM_PPMRL_CDUART0 (0x20)
+#define MCF_SCM_PPMRL_CDUART1 (0x40)
+#define MCF_SCM_PPMRL_CDUART2 (0x80)
+#define MCF_SCM_PPMRL_CDI2C0 (0x200)
+#define MCF_SCM_PPMRL_CDQSPI (0x400)
+#define MCF_SCM_PPMRL_CDI2C1 (0x800)
+#define MCF_SCM_PPMRL_CDDTIM0 (0x2000)
+#define MCF_SCM_PPMRL_CDDTIM1 (0x4000)
+#define MCF_SCM_PPMRL_CDDTIM2 (0x8000)
+#define MCF_SCM_PPMRL_CDDTIM3 (0x10000)
+#define MCF_SCM_PPMRL_CDINTC0 (0x20000)
+#define MCF_SCM_PPMRL_CDINTC1 (0x40000)
+#define MCF_SCM_PPMRL_CDFEC (0x200000)
+
+/* Bit definitions and macros for MCF_SCM_MPARK */
+#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)
+#define MCF_SCM_MPARK_PRKLAST (0x1000)
+#define MCF_SCM_MPARK_TIMEOUT (0x2000)
+#define MCF_SCM_MPARK_FIXED (0x4000)
+#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x3)<<0x10)
+#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)
+#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)
+#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x3)<<0x16)
+#define MCF_SCM_MPARK_BCR24BIT (0x1000000)
+#define MCF_SCM_MPARK_M2_P_EN (0x2000000)
+
+/* Bit definitions and macros for MCF_SCM_MPR */
+#define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_SCM_PPMRS */
+#define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)
+#define MCF_SCM_PPMRS_DISABLE_ALL (0x40)
+#define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)
+#define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)
+#define MCF_SCM_PPMRS_DISABLE_PWM (0x29)
+#define MCF_SCM_PPMRS_DISABLE_GPT (0x28)
+#define MCF_SCM_PPMRS_DISABLE_ADC (0x27)
+#define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)
+#define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)
+#define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)
+#define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)
+#define MCF_SCM_PPMRS_DISABLE_INTC (0x11)
+#define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)
+#define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)
+#define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)
+#define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)
+#define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)
+#define MCF_SCM_PPMRS_DISABLE_I2C (0x9)
+#define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)
+#define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)
+#define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)
+#define MCF_SCM_PPMRS_DISABLE_DMA (0x4)
+#define MCF_SCM_PPMRS_SET_CDG (0x1)
+
+/* Bit definitions and macros for MCF_SCM_PPMRC */
+#define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)
+#define MCF_SCM_PPMRC_ENABLE_ALL (0x40)
+#define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)
+#define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)
+#define MCF_SCM_PPMRC_ENABLE_PWM (0x29)
+#define MCF_SCM_PPMRC_ENABLE_GPT (0x28)
+#define MCF_SCM_PPMRC_ENABLE_ADC (0x27)
+#define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)
+#define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)
+#define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)
+#define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)
+#define MCF_SCM_PPMRC_ENABLE_INTC (0x11)
+#define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)
+#define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)
+#define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)
+#define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)
+#define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)
+#define MCF_SCM_PPMRC_ENABLE_I2C (0x9)
+#define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)
+#define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)
+#define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)
+#define MCF_SCM_PPMRC_ENABLE_DMA (0x4)
+#define MCF_SCM_PPMRC_CLEAR_CDG (0x1)
+
+/* Bit definitions and macros for MCF_SCM_IPSBMT */
+#define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)
+#define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)
+#define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)
+#define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)
+#define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)
+#define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)
+#define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)
+#define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)
+#define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)
+#define MCF_SCM_IPSBMT_BME (0x8)
+
+/* Bit definitions and macros for MCF_SCM_PACR */
+#define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)
+#define MCF_SCM_PACR_LOCK0 (0x8)
+#define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
+#define MCF_SCM_PACR_LOCK1 (0x80)
+
+/* Bit definitions and macros for MCF_SCM_PACR10 */
+#define MCF_SCM_PACR10_ACCESS_CTRL0(x) (((x)&0x7)<<0)
+#define MCF_SCM_PACR10_LOCK0 (0x8)
+#define MCF_SCM_PACR10_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
+#define MCF_SCM_PACR10_LOCK1 (0x80)
+
+/* Bit definitions and macros for MCF_SCM_GPACR */
+#define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)
+#define MCF_SCM_GPACR_LOCK (0x80)
+
+
+#endif /* __MCF52259_SCM_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_TMR.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_TMR.h new file mode 100644 index 00000000..3ba5cf95 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_TMR.h @@ -0,0 +1,89 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/02/26 Revision: 0.1
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_TMR_H__
+#define __MCF52259_TMR_H__
+
+
+/*********************************************************************
+*
+* Timer Module (TMR)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_TMR0_TMR (*(vuint16*)(0x40000400))
+#define MCF_TMR0_TRR (*(vuint16*)(0x40000404))
+#define MCF_TMR0_TCR (*(vuint16*)(0x40000408))
+#define MCF_TMR0_TCN (*(vuint16*)(0x4000040C))
+#define MCF_TMR0_TER (*(vuint8 *)(0x40000411))
+
+#define MCF_TMR1_TMR (*(vuint16*)(0x40000440))
+#define MCF_TMR1_TRR (*(vuint16*)(0x40000444))
+#define MCF_TMR1_TCR (*(vuint16*)(0x40000448))
+#define MCF_TMR1_TCN (*(vuint16*)(0x4000044C))
+#define MCF_TMR1_TER (*(vuint8 *)(0x40000451))
+
+#define MCF_TMR2_TMR (*(vuint16*)(0x40000480))
+#define MCF_TMR2_TRR (*(vuint16*)(0x40000484))
+#define MCF_TMR2_TCR (*(vuint16*)(0x40000488))
+#define MCF_TMR2_TCN (*(vuint16*)(0x4000048C))
+#define MCF_TMR2_TER (*(vuint8 *)(0x40000491))
+
+#define MCF_TMR3_TMR (*(vuint16*)(0x400004C0))
+#define MCF_TMR3_TRR (*(vuint16*)(0x400004C4))
+#define MCF_TMR3_TCR (*(vuint16*)(0x400004C8))
+#define MCF_TMR3_TCN (*(vuint16*)(0x400004CC))
+#define MCF_TMR3_TER (*(vuint8 *)(0x400004D1))
+
+#define MCF_TMR_TMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))
+#define MCF_TMR_TRR(x) (*(vuint16*)(0x40000404 + ((x)*0x40)))
+#define MCF_TMR_TCR(x) (*(vuint16*)(0x40000408 + ((x)*0x40)))
+#define MCF_TMR_TCN(x) (*(vuint16*)(0x4000040C + ((x)*0x40)))
+#define MCF_TMR_TER(x) (*(vuint8 *)(0x40000411 + ((x)*0x40)))
+
+
+/* Bit definitions and macros for MCF_TMR_TMR */
+#define MCF_TMR_TMR_RST (0x1)
+#define MCF_TMR_TMR_CLK(x) (((x)&0x3)<<0x1)
+#define MCF_TMR_TMR_CLK_STOP (0)
+#define MCF_TMR_TMR_CLK_SYSCLK (0x2)
+#define MCF_TMR_TMR_CLK_DIV16 (0x4)
+#define MCF_TMR_TMR_CLK_TIN (0x6)
+#define MCF_TMR_TMR_FRR (0x8)
+#define MCF_TMR_TMR_ORI (0x10)
+#define MCF_TMR_TMR_OM (0x20)
+#define MCF_TMR_TMR_CE(x) (((x)&0x3)<<0x6)
+#define MCF_TMR_TMR_CE_NONE (0)
+#define MCF_TMR_TMR_CE_RISE (0x40)
+#define MCF_TMR_TMR_CE_FALL (0x80)
+#define MCF_TMR_TMR_CE_ANY (0xC0)
+#define MCF_TMR_TMR_PS(x) (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_TMR_TRR */
+#define MCF_TMR_TRR_REF(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_TMR_TCR */
+#define MCF_TMR_TCR_CAP(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_TMR_TCN */
+#define MCF_TMR_TCN_COUNT(x) (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_TMR_TER */
+#define MCF_TMR_TER_CAP (0x1)
+#define MCF_TMR_TER_REF (0x2)
+
+
+#endif /* __MCF52259_TMR_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_UART.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_UART.h new file mode 100644 index 00000000..10d9d4c5 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_UART.h @@ -0,0 +1,202 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_UART_H__
+#define __MCF52259_UART_H__
+
+
+/*********************************************************************
+*
+* Universal Asynchronous Receiver Transmitter (UART)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_UART0_UMR1 (*(vuint8 *)(0x40000200))
+#define MCF_UART0_UMR2 (*(vuint8 *)(0x40000200))
+#define MCF_UART0_USR (*(vuint8 *)(0x40000204))
+#define MCF_UART0_UCSR (*(vuint8 *)(0x40000204))
+#define MCF_UART0_UCR (*(vuint8 *)(0x40000208))
+#define MCF_UART0_URB (*(vuint8 *)(0x4000020C))
+#define MCF_UART0_UTB (*(vuint8 *)(0x4000020C))
+#define MCF_UART0_UIPCR (*(vuint8 *)(0x40000210))
+#define MCF_UART0_UACR (*(vuint8 *)(0x40000210))
+#define MCF_UART0_UIMR (*(vuint8 *)(0x40000214))
+#define MCF_UART0_UISR (*(vuint8 *)(0x40000214))
+#define MCF_UART0_UBG1 (*(vuint8 *)(0x40000218))
+#define MCF_UART0_UBG2 (*(vuint8 *)(0x4000021C))
+#define MCF_UART0_UIP (*(vuint8 *)(0x40000234))
+#define MCF_UART0_UOP1 (*(vuint8 *)(0x40000238))
+#define MCF_UART0_UOP0 (*(vuint8 *)(0x4000023C))
+
+#define MCF_UART1_UMR1 (*(vuint8 *)(0x40000240))
+#define MCF_UART1_UMR2 (*(vuint8 *)(0x40000240))
+#define MCF_UART1_USR (*(vuint8 *)(0x40000244))
+#define MCF_UART1_UCSR (*(vuint8 *)(0x40000244))
+#define MCF_UART1_UCR (*(vuint8 *)(0x40000248))
+#define MCF_UART1_URB (*(vuint8 *)(0x4000024C))
+#define MCF_UART1_UTB (*(vuint8 *)(0x4000024C))
+#define MCF_UART1_UIPCR (*(vuint8 *)(0x40000250))
+#define MCF_UART1_UACR (*(vuint8 *)(0x40000250))
+#define MCF_UART1_UIMR (*(vuint8 *)(0x40000254))
+#define MCF_UART1_UISR (*(vuint8 *)(0x40000254))
+#define MCF_UART1_UBG1 (*(vuint8 *)(0x40000258))
+#define MCF_UART1_UBG2 (*(vuint8 *)(0x4000025C))
+#define MCF_UART1_UIP (*(vuint8 *)(0x40000274))
+#define MCF_UART1_UOP1 (*(vuint8 *)(0x40000278))
+#define MCF_UART1_UOP0 (*(vuint8 *)(0x4000027C))
+
+#define MCF_UART2_UMR1 (*(vuint8 *)(0x40000280))
+#define MCF_UART2_UMR2 (*(vuint8 *)(0x40000280))
+#define MCF_UART2_USR (*(vuint8 *)(0x40000284))
+#define MCF_UART2_UCSR (*(vuint8 *)(0x40000284))
+#define MCF_UART2_UCR (*(vuint8 *)(0x40000288))
+#define MCF_UART2_URB (*(vuint8 *)(0x4000028C))
+#define MCF_UART2_UTB (*(vuint8 *)(0x4000028C))
+#define MCF_UART2_UIPCR (*(vuint8 *)(0x40000290))
+#define MCF_UART2_UACR (*(vuint8 *)(0x40000290))
+#define MCF_UART2_UIMR (*(vuint8 *)(0x40000294))
+#define MCF_UART2_UISR (*(vuint8 *)(0x40000294))
+#define MCF_UART2_UBG1 (*(vuint8 *)(0x40000298))
+#define MCF_UART2_UBG2 (*(vuint8 *)(0x4000029C))
+#define MCF_UART2_UIP (*(vuint8 *)(0x400002B4))
+#define MCF_UART2_UOP1 (*(vuint8 *)(0x400002B8))
+#define MCF_UART2_UOP0 (*(vuint8 *)(0x400002BC))
+
+#define MCF_UART_UMR(x) (*(vuint8 *)(0x40000200 + ((x)*0x40)))
+#define MCF_UART_USR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))
+#define MCF_UART_UCSR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))
+#define MCF_UART_UCR(x) (*(vuint8 *)(0x40000208 + ((x)*0x40)))
+#define MCF_UART_URB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))
+#define MCF_UART_UTB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))
+#define MCF_UART_UIPCR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))
+#define MCF_UART_UACR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))
+#define MCF_UART_UIMR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))
+#define MCF_UART_UISR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))
+#define MCF_UART_UBG1(x) (*(vuint8 *)(0x40000218 + ((x)*0x40)))
+#define MCF_UART_UBG2(x) (*(vuint8 *)(0x4000021C + ((x)*0x40)))
+#define MCF_UART_UIP(x) (*(vuint8 *)(0x40000234 + ((x)*0x40)))
+#define MCF_UART_UOP1(x) (*(vuint8 *)(0x40000238 + ((x)*0x40)))
+#define MCF_UART_UOP0(x) (*(vuint8 *)(0x4000023C + ((x)*0x40)))
+
+/* Bit definitions and macros for MCF_UART_UMR */
+#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0)
+#define MCF_UART_UMR_BC_5 (0)
+#define MCF_UART_UMR_BC_6 (0x1)
+#define MCF_UART_UMR_BC_7 (0x2)
+#define MCF_UART_UMR_BC_8 (0x3)
+#define MCF_UART_UMR_PT (0x4)
+#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3)
+#define MCF_UART_UMR_ERR (0x20)
+#define MCF_UART_UMR_RXIRQ (0x40)
+#define MCF_UART_UMR_RXRTS (0x80)
+#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
+#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
+#define MCF_UART_UMR_PM_NONE (0x10)
+#define MCF_UART_UMR_PM_FORCE_HI (0xC)
+#define MCF_UART_UMR_PM_FORCE_LO (0x8)
+#define MCF_UART_UMR_PM_ODD (0x4)
+#define MCF_UART_UMR_PM_EVEN (0)
+#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0)
+#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7)
+#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8)
+#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF)
+#define MCF_UART_UMR_TXCTS (0x10)
+#define MCF_UART_UMR_TXRTS (0x20)
+#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6)
+#define MCF_UART_UMR_CM_NORMAL (0)
+#define MCF_UART_UMR_CM_ECHO (0x40)
+#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
+#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
+
+/* Bit definitions and macros for MCF_UART_USR */
+#define MCF_UART_USR_RXRDY (0x1)
+#define MCF_UART_USR_FFULL (0x2)
+#define MCF_UART_USR_TXRDY (0x4)
+#define MCF_UART_USR_TXEMP (0x8)
+#define MCF_UART_USR_OE (0x10)
+#define MCF_UART_USR_PE (0x20)
+#define MCF_UART_USR_FE (0x40)
+#define MCF_UART_USR_RB (0x80)
+
+/* Bit definitions and macros for MCF_UART_UCSR */
+#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0)
+#define MCF_UART_UCSR_TCS_SYS_CLK (0xD)
+#define MCF_UART_UCSR_TCS_CTM16 (0xE)
+#define MCF_UART_UCSR_TCS_CTM (0xF)
+#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4)
+#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
+#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
+#define MCF_UART_UCSR_RCS_CTM (0xF0)
+
+/* Bit definitions and macros for MCF_UART_UCR */
+#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0)
+#define MCF_UART_UCR_RX_ENABLED (0x1)
+#define MCF_UART_UCR_RX_DISABLED (0x2)
+#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2)
+#define MCF_UART_UCR_TX_ENABLED (0x4)
+#define MCF_UART_UCR_TX_DISABLED (0x8)
+#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4)
+#define MCF_UART_UCR_NONE (0)
+#define MCF_UART_UCR_RESET_MR (0x10)
+#define MCF_UART_UCR_RESET_RX (0x20)
+#define MCF_UART_UCR_RESET_TX (0x30)
+#define MCF_UART_UCR_RESET_ERROR (0x40)
+#define MCF_UART_UCR_RESET_BKCHGINT (0x50)
+#define MCF_UART_UCR_START_BREAK (0x60)
+#define MCF_UART_UCR_STOP_BREAK (0x70)
+
+/* Bit definitions and macros for MCF_UART_URB */
+#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_UART_UTB */
+#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_UART_UIPCR */
+#define MCF_UART_UIPCR_CTS (0x1)
+#define MCF_UART_UIPCR_COS (0x10)
+
+/* Bit definitions and macros for MCF_UART_UACR */
+#define MCF_UART_UACR_IEC (0x1)
+
+/* Bit definitions and macros for MCF_UART_UIMR */
+#define MCF_UART_UIMR_TXRDY (0x1)
+#define MCF_UART_UIMR_FFULL_RXRDY (0x2)
+#define MCF_UART_UIMR_DB (0x4)
+#define MCF_UART_UIMR_COS (0x80)
+
+/* Bit definitions and macros for MCF_UART_UISR */
+#define MCF_UART_UISR_TXRDY (0x1)
+#define MCF_UART_UISR_FFULL_RXRDY (0x2)
+#define MCF_UART_UISR_DB (0x4)
+#define MCF_UART_UISR_COS (0x80)
+
+/* Bit definitions and macros for MCF_UART_UBG1 */
+#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_UART_UBG2 */
+#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_UART_UIP */
+#define MCF_UART_UIP_CTS (0x1)
+
+/* Bit definitions and macros for MCF_UART_UOP1 */
+#define MCF_UART_UOP1_RTS (0x1)
+
+/* Bit definitions and macros for MCF_UART_UOP0 */
+#define MCF_UART_UOP0_RTS (0x1)
+
+
+#endif /* __MCF52259_UART_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_USB_OTG.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_USB_OTG.h new file mode 100644 index 00000000..001c2401 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/MCF52259_USB_OTG.h @@ -0,0 +1,268 @@ +/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/04/17 Revision: 0.2
+ *
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008
+ * UNIS, spol. s r.o.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http : www.processorexpert.com
+ * mail : info@processorexpert.com
+ */
+
+#ifndef __MCF52259_USB_OTG_H__
+#define __MCF52259_USB_OTG_H__
+
+
+/*********************************************************************
+*
+* Universal Serial Bus - OTG Controller (USB_OTG)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_USB_OTG_PER_ID (*(vuint8 *)(&__IPSBAR[0x1C0000]))
+#define MCF_USB_OTG_ID_COMP (*(vuint8 *)(&__IPSBAR[0x1C0004]))
+#define MCF_USB_OTG_REV (*(vuint8 *)(&__IPSBAR[0x1C0008]))
+#define MCF_USB_OTG_ADD_INFO (*(vuint8 *)(&__IPSBAR[0x1C000C]))
+#define MCF_USB_OTG_OTG_INT_STAT (*(vuint8 *)(&__IPSBAR[0x1C0010]))
+#define MCF_USB_OTG_OTG_INT_EN (*(vuint8 *)(&__IPSBAR[0x1C0014]))
+#define MCF_USB_OTG_OTG_STAT (*(vuint8 *)(&__IPSBAR[0x1C0018]))
+#define MCF_USB_OTG_OTG_CTRL (*(vuint8 *)(&__IPSBAR[0x1C001C]))
+#define MCF_USB_OTG_INT_STAT (*(vuint8 *)(&__IPSBAR[0x1C0080]))
+#define MCF_USB_OTG_INT_ENB (*(vuint8 *)(&__IPSBAR[0x1C0084]))
+#define MCF_USB_OTG_ERR_STAT (*(vuint8 *)(&__IPSBAR[0x1C0088]))
+#define MCF_USB_OTG_ERR_ENB (*(vuint8 *)(&__IPSBAR[0x1C008C]))
+#define MCF_USB_OTG_STAT (*(vuint8 *)(&__IPSBAR[0x1C0090]))
+#define MCF_USB_OTG_CTL (*(vuint8 *)(&__IPSBAR[0x1C0094]))
+#define MCF_USB_OTG_ADDR (*(vuint8 *)(&__IPSBAR[0x1C0098]))
+#define MCF_USB_OTG_BDT_PAGE_01 (*(vuint8 *)(&__IPSBAR[0x1C009C]))
+#define MCF_USB_OTG_FRM_NUML (*(vuint8 *)(&__IPSBAR[0x1C00A0]))
+#define MCF_USB_OTG_FRM_NUMH (*(vuint8 *)(&__IPSBAR[0x1C00A4]))
+#define MCF_USB_OTG_TOKEN (*(vuint8 *)(&__IPSBAR[0x1C00A8]))
+#define MCF_USB_OTG_SOF_THLD (*(vuint8 *)(&__IPSBAR[0x1C00AC]))
+#define MCF_USB_OTG_BDT_PAGE_02 (*(vuint8 *)(&__IPSBAR[0x1C00B0]))
+#define MCF_USB_OTG_BDT_PAGE_03 (*(vuint8 *)(&__IPSBAR[0x1C00B4]))
+#define MCF_USB_OTG_ENDPT0 (*(vuint8 *)(&__IPSBAR[0x1C00C0]))
+#define MCF_USB_OTG_ENDPT1 (*(vuint8 *)(&__IPSBAR[0x1C00C4]))
+#define MCF_USB_OTG_ENDPT2 (*(vuint8 *)(&__IPSBAR[0x1C00C8]))
+#define MCF_USB_OTG_ENDPT3 (*(vuint8 *)(&__IPSBAR[0x1C00CC]))
+#define MCF_USB_OTG_ENDPT4 (*(vuint8 *)(&__IPSBAR[0x1C00D0]))
+#define MCF_USB_OTG_ENDPT5 (*(vuint8 *)(&__IPSBAR[0x1C00D4]))
+#define MCF_USB_OTG_ENDPT6 (*(vuint8 *)(&__IPSBAR[0x1C00D8]))
+#define MCF_USB_OTG_ENDPT7 (*(vuint8 *)(&__IPSBAR[0x1C00DC]))
+#define MCF_USB_OTG_ENDPT8 (*(vuint8 *)(&__IPSBAR[0x1C00E0]))
+#define MCF_USB_OTG_ENDPT9 (*(vuint8 *)(&__IPSBAR[0x1C00E4]))
+#define MCF_USB_OTG_ENDPT10 (*(vuint8 *)(&__IPSBAR[0x1C00E8]))
+#define MCF_USB_OTG_ENDPT11 (*(vuint8 *)(&__IPSBAR[0x1C00EC]))
+#define MCF_USB_OTG_ENDPT12 (*(vuint8 *)(&__IPSBAR[0x1C00F0]))
+#define MCF_USB_OTG_ENDPT13 (*(vuint8 *)(&__IPSBAR[0x1C00F4]))
+#define MCF_USB_OTG_ENDPT14 (*(vuint8 *)(&__IPSBAR[0x1C00F8]))
+#define MCF_USB_OTG_ENDPT15 (*(vuint8 *)(&__IPSBAR[0x1C00FC]))
+#define MCF_USB_OTG_USB_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0100]))
+#define MCF_USB_OTG_USB_OTG_OBSERVE (*(vuint8 *)(&__IPSBAR[0x1C0104]))
+#define MCF_USB_OTG_USB_OTG_CONTROL (*(vuint8 *)(&__IPSBAR[0x1C0108]))
+#define MCF_USB_OTG_ENDPT(x) (*(vuint8 *)(&__IPSBAR[0x1C00C0 + ((x)*0x4)]))
+
+/* Other macros */
+#define MCF_USB_OTG_FRM_NUM (MCF_USB_OTG_INT_STAT=MCF_USB_OTG_INT_STAT_SOF_TOK ,MCF_USB_OTG_FRM_NUML | (((vuint16)MCF_USB_OTG_FRM_NUMH)<<8))
+
+
+/* Bit definitions and macros for MCF_USB_OTG_PER_ID */
+#define MCF_USB_OTG_PER_ID_ID(x) (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_USB_OTG_ID_COMP */
+#define MCF_USB_OTG_ID_COMP_NID(x) (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_USB_OTG_REV */
+#define MCF_USB_OTG_REV_REV(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_OTG_ADD_INFO */
+#define MCF_USB_OTG_ADD_INFO_IEHOST (0x1)
+#define MCF_USB_OTG_ADD_INFO_IRQ_NUM(x) (((x)&0x1F)<<0x3)
+
+/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_STAT */
+#define MCF_USB_OTG_OTG_INT_STAT_A_VBUS_CHG (0x1)
+#define MCF_USB_OTG_OTG_INT_STAT_B_SESS_CHG (0x4)
+#define MCF_USB_OTG_OTG_INT_STAT_SESS_VLD_CHG (0x8)
+#define MCF_USB_OTG_OTG_INT_STAT_LINE_STATE_CHG (0x20)
+#define MCF_USB_OTG_OTG_INT_STAT_1_MSEC (0x40)
+#define MCF_USB_OTG_OTG_INT_STAT_ID_CHG (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_EN */
+#define MCF_USB_OTG_OTG_INT_EN_A_VBUS_EN (0x1)
+#define MCF_USB_OTG_OTG_INT_EN_B_SESS_EN (0x4)
+#define MCF_USB_OTG_OTG_INT_EN_SESS_VLD_EN (0x8)
+#define MCF_USB_OTG_OTG_INT_EN_LINE_STATE_EN (0x20)
+#define MCF_USB_OTG_OTG_INT_EN_1_MSEC_EN (0x40)
+#define MCF_USB_OTG_OTG_INT_EN_ID_EN (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_OTG_STAT */
+#define MCF_USB_OTG_OTG_STAT_A_VBUS_VLD (0x1)
+#define MCF_USB_OTG_OTG_STAT_B_SESS_END (0x4)
+#define MCF_USB_OTG_OTG_STAT_SESS_VLD (0x8)
+#define MCF_USB_OTG_OTG_STAT_LINE_STATE_STABLE (0x20)
+#define MCF_USB_OTG_OTG_STAT_1_MSEC_EN (0x40)
+#define MCF_USB_OTG_OTG_STAT_ID (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_OTG_CTRL */
+#define MCF_USB_OTG_OTG_CTRL_VBUS_DSCHG (0x1)
+#define MCF_USB_OTG_OTG_CTRL_VBUS_CHG (0x2)
+#define MCF_USB_OTG_OTG_CTRL_OTG_EN (0x4)
+#define MCF_USB_OTG_OTG_CTRL_VBUS_ON (0x8)
+#define MCF_USB_OTG_OTG_CTRL_DM_LOW (0x10)
+#define MCF_USB_OTG_OTG_CTRL_DP_LOW (0x20)
+#define MCF_USB_OTG_OTG_CTRL_DP_HIGH (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_INT_STAT */
+#define MCF_USB_OTG_INT_STAT_USB_RST (0x1)
+#define MCF_USB_OTG_INT_STAT_ERROR (0x2)
+#define MCF_USB_OTG_INT_STAT_SOF_TOK (0x4)
+#define MCF_USB_OTG_INT_STAT_TOK_DNE (0x8)
+#define MCF_USB_OTG_INT_STAT_SLEEP (0x10)
+#define MCF_USB_OTG_INT_STAT_RESUME (0x20)
+#define MCF_USB_OTG_INT_STAT_ATTACH (0x40)
+#define MCF_USB_OTG_INT_STAT_STALL (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_INT_ENB */
+#define MCF_USB_OTG_INT_ENB_USB_RST_EN (0x1)
+#define MCF_USB_OTG_INT_ENB_ERROR_EN (0x2)
+#define MCF_USB_OTG_INT_ENB_SOF_TOK_EN (0x4)
+#define MCF_USB_OTG_INT_ENB_TOK_DNE_EN (0x8)
+#define MCF_USB_OTG_INT_ENB_SLEEP_EN (0x10)
+#define MCF_USB_OTG_INT_ENB_RESUME_EN (0x20)
+#define MCF_USB_OTG_INT_ENB_ATTACH_EN (0x40)
+#define MCF_USB_OTG_INT_ENB_STALL_EN (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_ERR_STAT */
+#define MCF_USB_OTG_ERR_STAT_PID_ERR (0x1)
+#define MCF_USB_OTG_ERR_STAT_CRC5_EOF (0x2)
+#define MCF_USB_OTG_ERR_STAT_CRC16 (0x4)
+#define MCF_USB_OTG_ERR_STAT_DFN8 (0x8)
+#define MCF_USB_OTG_ERR_STAT_BTO_ERR (0x10)
+#define MCF_USB_OTG_ERR_STAT_DMA_ERR (0x20)
+#define MCF_USB_OTG_ERR_STAT_BTS_ERR (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_ERR_ENB */
+#define MCF_USB_OTG_ERR_ENB_PID_ERR_EN (0x1)
+#define MCF_USB_OTG_ERR_ENB_CRC5_EOF_EN (0x2)
+#define MCF_USB_OTG_ERR_ENB_CRC16_EN (0x4)
+#define MCF_USB_OTG_ERR_ENB_DFN8_EN (0x8)
+#define MCF_USB_OTG_ERR_ENB_BTO_ERR_EN (0x10)
+#define MCF_USB_OTG_ERR_ENB_DMA_ERR_EN (0x20)
+#define MCF_USB_OTG_ERR_ENB_BTS_ERR_EN (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_STAT */
+#define MCF_USB_OTG_STAT_ODD (0x4)
+#define MCF_USB_OTG_STAT_TX (0x8)
+#define MCF_USB_OTG_STAT_ENDP(x) (((x)&0xF)<<0x4)
+
+/* Bit definitions and macros for MCF_USB_OTG_CTL */
+#define MCF_USB_OTG_CTL_USB_EN_SOF_EN (0x1)
+#define MCF_USB_OTG_CTL_ODD_RST (0x2)
+#define MCF_USB_OTG_CTL_RESUME (0x4)
+#define MCF_USB_OTG_CTL_HOST_MODE_EN (0x8)
+#define MCF_USB_OTG_CTL_RESET (0x10)
+#define MCF_USB_OTG_CTL_TXSUSPEND_TOKENBUSY (0x20)
+#define MCF_USB_OTG_CTL_SE0 (0x40)
+#define MCF_USB_OTG_CTL_JSTATE (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_ADDR */
+#define MCF_USB_OTG_ADDR_ADDR(x) (((x)&0x7F)<<0)
+#define MCF_USB_OTG_ADDR_LS_EN (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_01 */
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA9 (0x2)
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA10 (0x4)
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA11 (0x8)
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA12 (0x10)
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA13 (0x20)
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA14 (0x40)
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA15 (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_FRM_NUML */
+#define MCF_USB_OTG_FRM_NUML_FRM0 (0x1)
+#define MCF_USB_OTG_FRM_NUML_FRM1 (0x2)
+#define MCF_USB_OTG_FRM_NUML_FRM2 (0x4)
+#define MCF_USB_OTG_FRM_NUML_FRM3 (0x8)
+#define MCF_USB_OTG_FRM_NUML_FRM4 (0x10)
+#define MCF_USB_OTG_FRM_NUML_FRM5 (0x20)
+#define MCF_USB_OTG_FRM_NUML_FRM6 (0x40)
+#define MCF_USB_OTG_FRM_NUML_FRM7 (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_FRM_NUMH */
+#define MCF_USB_OTG_FRM_NUMH_FRM8 (0x1)
+#define MCF_USB_OTG_FRM_NUMH_FRM9 (0x2)
+#define MCF_USB_OTG_FRM_NUMH_FRM10 (0x4)
+
+/* Bit definitions and macros for MCF_USB_OTG_TOKEN */
+#define MCF_USB_OTG_TOKEN_TOKEN_ENDPT(x) (((x)&0xF)<<0)
+#define MCF_USB_OTG_TOKEN_TOKEN_PID(x) (((x)&0xF)<<0x4)
+#define MCF_USB_OTG_TOKEN_TOKEN_PID_OUT (0x10)
+#define MCF_USB_OTG_TOKEN_TOKEN_PID_IN (0x90)
+#define MCF_USB_OTG_TOKEN_TOKEN_PID_SETUP (0xD0)
+
+/* Bit definitions and macros for MCF_USB_OTG_SOF_THLD */
+#define MCF_USB_OTG_SOF_THLD_CNT0 (0x1)
+#define MCF_USB_OTG_SOF_THLD_CNT1 (0x2)
+#define MCF_USB_OTG_SOF_THLD_CNT2 (0x4)
+#define MCF_USB_OTG_SOF_THLD_CNT3 (0x8)
+#define MCF_USB_OTG_SOF_THLD_CNT4 (0x10)
+#define MCF_USB_OTG_SOF_THLD_CNT5 (0x20)
+#define MCF_USB_OTG_SOF_THLD_CNT6 (0x40)
+#define MCF_USB_OTG_SOF_THLD_CNT7 (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_02 */
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA16 (0x1)
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA17 (0x2)
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA18 (0x4)
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA19 (0x8)
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA20 (0x10)
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA21 (0x20)
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA22 (0x40)
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA23 (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_03 */
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA24 (0x1)
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA25 (0x2)
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA26 (0x4)
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA27 (0x8)
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA28 (0x10)
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA29 (0x20)
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA30 (0x40)
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA31 (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_ENDPT */
+#define MCF_USB_OTG_ENDPT_EP_HSHK (0x1)
+#define MCF_USB_OTG_ENDPT_EP_STALL (0x2)
+#define MCF_USB_OTG_ENDPT_EP_TX_EN (0x4)
+#define MCF_USB_OTG_ENDPT_EP_RX_EN (0x8)
+#define MCF_USB_OTG_ENDPT_EP_CTL_DIS (0x10)
+#define MCF_USB_OTG_ENDPT_RETRY_DIS (0x40)
+#define MCF_USB_OTG_ENDPT_HOST_WO_HUB (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_USB_CTRL */
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC(x) (((x)&0x3)<<0)
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC_ALTCLK (0)
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC_OSCCLK (0x1)
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC_SYSCLK (0x3)
+#define MCF_USB_OTG_USB_CTRL_PDE (0x40)
+#define MCF_USB_OTG_USB_CTRL_SUSP (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_OBSERVE */
+#define MCF_USB_OTG_USB_OTG_OBSERVE_DM_PD (0x10)
+#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PD (0x40)
+#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PU (0x80)
+
+/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_CONTROL */
+#define MCF_USB_OTG_USB_OTG_CONTROL_SESSEND (0x1)
+#define MCF_USB_OTG_USB_OTG_CONTROL_SESSVLD (0x2)
+#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSVLD (0x4)
+#define MCF_USB_OTG_USB_OTG_CONTROL_ID (0x8)
+#define MCF_USB_OTG_USB_OTG_CONTROL_DPPULLUP_NONOTG (0x10)
+
+
+#endif /* __MCF52259_USB_OTG_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/common.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/common.h new file mode 100644 index 00000000..c3886a97 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/common.h @@ -0,0 +1,96 @@ +/*
+ * File: common.h
+ * Purpose: File to be included by all project files
+ *
+ * Notes:
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+/********************************************************************/
+
+/*
+ * Debug prints ON (#define) or OFF (#undef)
+ */
+#undef DEBUG_PRINT
+#undef DEBUG_PRINT_D0D1
+
+/*
+ * Include the generic CPU header file
+ */
+#include "mcf5xxx.h"
+
+/*
+ * Include the specific CPU header file
+ */
+#include "mcf5225x.h"
+
+#include "mcf5225x_evb.h"
+
+/*
+ * MetroWerks looks for an underscore prepended to C function names
+ */
+#define _UNDERSCORE_
+
+/*
+ * The source uses __interrupt__ to identify a function as
+ * an interrupt or exception handler. Codewarrior uses
+ * __declspec(interrupt), so we are appeasing it like this.
+ */
+#define __interrupt__ __declspec(interrupt)
+
+/*
+ * Force functions to return values in D0
+ */
+#pragma pointers_in_D0
+
+/*
+ * Provide a few assembly instructions for C level routines
+ */
+#define halt() asm( halt)
+#define nop() asm( nop)
+#define tpf() asm( tpf)
+#define stop_2700() asm( stop #0x2700)
+#define stop_2600() asm( stop #0x2600)
+#define stop_2500() asm( stop #0x2500)
+#define stop_2400() asm( stop #0x2400)
+#define stop_2300() asm( stop #0x2300)
+#define stop_2200() asm( stop #0x2200)
+#define stop_2100() asm( stop #0x2100)
+#define stop_2000() asm( stop #0x2000)
+
+/*
+ * Define custom sections for relocating code, data, and constants
+ */
+#pragma define_section relocate_code ".relocate_code" far_absolute RX
+#pragma define_section relocate_data ".relocate_data" far_absolute RW
+#pragma define_section relocate_const ".relocate_const" far_absolute R
+#define __relocate_code__ __declspec(relocate_code)
+#define __relocate_data__ __declspec(relocate_data)
+#define __relocate_const__ __declspec(relocate_const)
+
+/*
+ * Include common utilities
+ */
+void assert_failed(char *, int);
+
+#ifdef DEBUG_PRINT
+#define ASSERT(expr) \
+ if (!(expr)) \
+ assert_failed(__FILE__, __LINE__)
+#else
+#define ASSERT(expr)
+#endif
+
+//#include "assert.h"
+//#include "io.h"
+//#include "stdlib.h"
+
+
+/********************************************************************/
+
+#endif /* _COMMON_H_ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/mcf5225x.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/mcf5225x.h new file mode 100644 index 00000000..57a23232 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/mcf5225x.h @@ -0,0 +1,48 @@ +/*
+ * File: mcf5225x.h
+ * Purpose: Register and bit definitions
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#ifndef __MCF5225x_H__
+#define __MCF5225x_H__
+
+/********************************************************************/
+/*
+ * 5225x includes
+ */
+
+#include "MCF52259_SCM.h"
+#include "MCF52259_FBCS.h"
+#include "MCF52259_DMA.h"
+#include "MCF52259_UART.h"
+#include "MCF52259_I2C.h"
+#include "MCF52259_QSPI.h"
+#include "MCF52259_DTIM.h"
+#include "MCF52259_INTC.h"
+#include "MCF52259_FEC.h"
+#include "MCF52259_GPIO.h"
+#include "MCF52259_PAD.h"
+#include "MCF52259_RCM.h"
+#include "MCF52259_CCM.h"
+#include "MCF52259_PMM.h"
+#include "MCF52259_CLOCK.h"
+#include "MCF52259_EPORT.h"
+#include "MCF52259_BWT.h"
+#include "MCF52259_PIT.h"
+#include "MCF52259_FlexCAN.h"
+#include "MCF52259_CANMB.h"
+#include "MCF52259_RTC.h"
+#include "MCF52259_ADC.h"
+#include "MCF52259_GPT.h"
+#include "MCF52259_PWM.h"
+#include "MCF52259_USB_OTG.h"
+#include "MCF52259_CFM.h"
+#include "MCF52259_RNGA.h"
+
+
+/********************************************************************/
+
+#endif /* __MCF5225x_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/mcf5225x_evb.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/mcf5225x_evb.h new file mode 100644 index 00000000..becaebc8 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/mcf5225x_evb.h @@ -0,0 +1,95 @@ +/*
+ * File: m5225x_evb.h
+ * Purpose: Evaluation board definitions and memory map information
+ *
+ * Notes:
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#ifndef _M5225xEVB_H
+#define _M5225xEVB_H
+
+#define COLDFIRE_MAC_ADDRESS {0x00, 0x04, 0x9f, 0x00, 0xab, 0x2b}
+
+/********************************************************************/
+
+//#include "mcf5xxx.h"
+
+/********************************************************************/
+#define LED0_TOGGLE MCF_GPIO_PORTTC = (uint8)(MCF_GPIO_PORTTC ^ MCF_GPIO_PORTTC_PORTTC0)
+
+/*
+ * Debug prints ON (#undef) or OFF (#define)
+ */
+#undef DEBUG
+
+/*
+ * System Bus Clock Info
+ */
+
+
+#define SYSTEM_CLOCK 80 /* system bus frequency in MHz */
+//#define PERIOD 12.5 /* system bus period in ns */
+#define TERMINAL_BAUD 19200
+#define UART_BAUD TERMINAL_BAUD /* 19200*/
+
+#define TERMINAL_PORT 0
+#define REF_CLK_MHZ 48
+#define SYS_CLK_MHZ SYSTEM_CLOCK
+#define REF_CLK_KHZ (REF_CLK_MHZ * 1000)
+#define SYS_CLK_KHZ (SYS_CLK_MHZ * 1000)
+
+/*
+ * Memory map definitions from linker command files
+ */
+
+extern uint8 __IPSBAR[];
+extern uint8 __SRAM[];
+extern uint8 __FLASH[];
+extern uint8 __SRAM_SIZE[];
+extern uint8 __FLASH_SIZE[];
+extern uint8 __DATA_ROM[];
+extern uint8 __DATA_RAM[];
+extern uint8 __DATA_END[];
+extern uint8 __BSS_START[];
+extern uint8 __BSS_END[];
+extern uint32 VECTOR_TABLE[];
+extern uint32 __VECTOR_RAM[];
+
+
+/*
+ * Memory Map Info
+ */
+#define IPSBAR_ADDRESS (uint32)__IPSBAR
+
+#define SRAM_ADDRESS (uint32)__SRAM
+#define SRAM_SIZE (uint32)__SRAM_SIZE
+
+#define FLASH_ADDRESS (uint32)__FLASH
+#define FLASH_SIZE (uint32)__FLASH_SIZE
+
+/*
+ * Interrupt Controller Definitions
+ */
+#define TIMER_NETWORK_LEVEL 3
+#define USB_NETWORK_LEVEL 1
+
+/*
+ * Timer period info
+ */
+
+ /* 1 sec / max timeout */
+#define TIMER_NETWORK_PERIOD 1000000000/0x10000
+
+/*
+ * Board specific function prototypes
+ */
+
+void leds_init();
+void board_led_display(uint8 number);
+
+/********************************************************************/
+
+#endif /* _M5225xEVB_H */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/mcf5xxx.h b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/mcf5xxx.h new file mode 100644 index 00000000..60b65261 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/Freescale_Headers/mcf5xxx.h @@ -0,0 +1,282 @@ +/*
+ * File: mcf5xxx.h
+ * Purpose: Definitions common to all ColdFire processors
+ *
+ * Notes:
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#ifndef _CPU_MCF5XXX_H
+#define _CPU_MCF5XXX_H
+
+/***********************************************************************/
+/*
+ * Misc. Defines
+ */
+#ifdef FALSE
+#undef FALSE
+#endif
+#define FALSE (0)
+
+#ifdef TRUE
+#undef TRUE
+#endif
+#define TRUE (1)
+
+#ifdef NULL
+#undef NULL
+#endif
+#define NULL (0)
+
+#ifdef ON
+#undef ON
+#endif
+#define ON (1)
+
+#ifdef OFF
+#undef OFF
+#endif
+#define OFF (0)
+
+/***********************************************************************/
+/*
+ * The basic data types
+ */
+typedef unsigned char uint8; /* 8 bits */
+typedef unsigned short int uint16; /* 16 bits */
+typedef unsigned long int uint32; /* 32 bits */
+
+typedef char int8; /* 8 bits */
+typedef short int int16; /* 16 bits */
+typedef int int32; /* 32 bits */
+
+typedef volatile int8 vint8; /* 8 bits */
+typedef volatile int16 vint16; /* 16 bits */
+typedef volatile int32 vint32; /* 32 bits */
+
+typedef volatile uint8 vuint8; /* 8 bits */
+typedef volatile uint16 vuint16; /* 16 bits */
+typedef volatile uint32 vuint32; /* 32 bits */
+
+/***********************************************************************/
+/*
+ * Common M68K & ColdFire definitions
+ */
+#define ADDRESS uint32
+#define INSTRUCTION uint16
+#define ILLEGAL 0x4AFC
+#define CPU_WORD_SIZE 16
+
+/* Status Register */
+#define MCF5XXX_SR_T (0x8000)
+#define MCF5XXX_SR_S (0x2000)
+#define MCF5XXX_SR_M (0x1000)
+#define MCF5XXX_SR_IPL (0x0700)
+#define MCF5XXX_SR_IPL_0 (0x0000)
+#define MCF5XXX_SR_IPL_1 (0x0100)
+#define MCF5XXX_SR_IPL_2 (0x0200)
+#define MCF5XXX_SR_IPL_3 (0x0300)
+#define MCF5XXX_SR_IPL_4 (0x0400)
+#define MCF5XXX_SR_IPL_5 (0x0500)
+#define MCF5XXX_SR_IPL_6 (0x0600)
+#define MCF5XXX_SR_IPL_7 (0x0700)
+#define MCF5XXX_SR_X (0x0010)
+#define MCF5XXX_SR_N (0x0008)
+#define MCF5XXX_SR_Z (0x0004)
+#define MCF5XXX_SR_V (0x0002)
+#define MCF5XXX_SR_C (0x0001)
+
+/* Cache Control Register */
+#define MCF5XXX_CACR_CENB (0x80000000)
+#define MCF5XXX_CACR_DEC (0x80000000)
+#define MCF5XXX_CACR_DW (0x40000000)
+#define MCF5XXX_CACR_DESB (0x20000000)
+#define MCF5XXX_CACR_CPDI (0x10000000)
+#define MCF5XXX_CACR_DDPI (0x10000000)
+#define MCF5XXX_CACR_CPD (0x10000000)
+#define MCF5XXX_CACR_CFRZ (0x08000000)
+#define MCF5XXX_CACR_DHLCK (0x08000000)
+#define MCF5XXX_CACR_DDCM_WT (0x00000000)
+#define MCF5XXX_CACR_DDCM_CB (0x02000000)
+#define MCF5XXX_CACR_DDCM_IP (0x04000000)
+#define MCF5XXX_CACR_DDCM_II (0x06000000)
+#define MCF5XXX_CACR_CINV (0x01000000)
+#define MCF5XXX_CACR_DCINVA (0x01000000)
+#define MCF5XXX_CACR_DIDI (0x00800000)
+#define MCF5XXX_CACR_DDSP (0x00800000)
+#define MCF5XXX_CACR_DISD (0x00400000)
+#define MCF5XXX_CACR_INVI (0x00200000)
+#define MCF5XXX_CACR_INVD (0x00100000)
+#define MCF5XXX_CACR_BEC (0x00080000)
+#define MCF5XXX_CACR_BCINVA (0x00040000)
+#define MCF5XXX_CACR_IEC (0x00008000)
+#define MCF5XXX_CACR_DNFB (0x00002000)
+#define MCF5XXX_CACR_IDPI (0x00001000)
+#define MCF5XXX_CACR_IHLCK (0x00000800)
+#define MCF5XXX_CACR_CEIB (0x00000400)
+#define MCF5XXX_CACR_IDCM (0x00000400)
+#define MCF5XXX_CACR_DCM_WR (0x00000000)
+#define MCF5XXX_CACR_DCM_CB (0x00000100)
+#define MCF5XXX_CACR_DCM_IP (0x00000200)
+#define MCF5XXX_CACR_DCM (0x00000200)
+#define MCF5XXX_CACR_DCM_II (0x00000300)
+#define MCF5XXX_CACR_DBWE (0x00000100)
+#define MCF5XXX_CACR_ICINVA (0x00000100)
+#define MCF5XXX_CACR_IDSP (0x00000080)
+#define MCF5XXX_CACR_DWP (0x00000020)
+#define MCF5XXX_CACR_EUSP (0x00000020)
+#define MCF5XXX_CACR_EUST (0x00000020)
+#define MCF5XXX_CACR_DF (0x00000010)
+#define MCF5XXX_CACR_CLNF_00 (0x00000000)
+#define MCF5XXX_CACR_CLNF_01 (0x00000002)
+#define MCF5XXX_CACR_CLNF_10 (0x00000004)
+#define MCF5XXX_CACR_CLNF_11 (0x00000006)
+
+/* Access Control Register */
+#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
+#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
+#define MCF5XXX_ACR_AM_4G (0x00FF0000)
+#define MCF5XXX_ACR_AM_2G (0x007F0000)
+#define MCF5XXX_ACR_AM_1G (0x003F0000)
+#define MCF5XXX_ACR_AM_1024M (0x003F0000)
+#define MCF5XXX_ACR_AM_512M (0x001F0000)
+#define MCF5XXX_ACR_AM_256M (0x000F0000)
+#define MCF5XXX_ACR_AM_128M (0x00070000)
+#define MCF5XXX_ACR_AM_64M (0x00030000)
+#define MCF5XXX_ACR_AM_32M (0x00010000)
+#define MCF5XXX_ACR_AM_16M (0x00000000)
+#define MCF5XXX_ACR_EN (0x00008000)
+#define MCF5XXX_ACR_SM_USER (0x00000000)
+#define MCF5XXX_ACR_SM_SUPER (0x00002000)
+#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
+#define MCF5XXX_ACR_ENIB (0x00000080)
+#define MCF5XXX_ACR_CM (0x00000040)
+#define MCF5XXX_ACR_DCM_WR (0x00000000)
+#define MCF5XXX_ACR_DCM_CB (0x00000020)
+#define MCF5XXX_ACR_DCM_IP (0x00000040)
+#define MCF5XXX_ACR_DCM_II (0x00000060)
+#define MCF5XXX_ACR_CM (0x00000040)
+#define MCF5XXX_ACR_BWE (0x00000020)
+#define MCF5XXX_ACR_WP (0x00000004)
+
+/* RAM Base Address Register */
+#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
+#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
+#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
+#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
+#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
+#define MCF5XXX_RAMBAR_WP (0x00000100)
+#define MCF5XXX_RAMBAR_CI (0x00000020)
+#define MCF5XXX_RAMBAR_SC (0x00000010)
+#define MCF5XXX_RAMBAR_SD (0x00000008)
+#define MCF5XXX_RAMBAR_UC (0x00000004)
+#define MCF5XXX_RAMBAR_UD (0x00000002)
+#define MCF5XXX_RAMBAR_V (0x00000001)
+
+/* Read macros for D0/D1 reset values */
+#define MCF5XXX_D0_PF(x) (((x)&0xFF000000)>>24)
+#define MCF5XXX_D0_VER(x) (((x)&0x00F00000)>>20)
+#define MCF5XXX_D0_REV(x) (((x)&0x000F0000)>>16)
+#define MCF5XXX_D0_MAC(x) ((x)&0x00008000)
+#define MCF5XXX_D0_DIV(x) ((x)&0x00004000)
+#define MCF5XXX_D0_EMAC(x) ((x)&0x00002000)
+#define MCF5XXX_D0_FPU(x) ((x)&0x00001000)
+#define MCF5XXX_D0_MMU(x) ((x)&0x00000800)
+#define MCF5XXX_D0_ISA(x) (((x)&0x000000F0)>>4)
+#define MCF5XXX_D0_DEBUG(x) (((x)&0x0000000F)>>0)
+#define MCF5XXX_D1_CL(x) (((x)&0xC0000000)>>30)
+#define MCF5XXX_D1_ICA(x) (((x)&0x30000000)>>28)
+#define MCF5XXX_D1_ICSIZ(x) (((x)&0x0F000000)>>24)
+#define MCF5XXX_D1_RAM0SIZ(x) (((x)&0x00F00000)>>20)
+#define MCF5XXX_D1_ROM0SIZ(x) (((x)&0x000F0000)>>16)
+#define MCF5XXX_D1_BUSW(x) (((x)&0x0000C000)>>14)
+#define MCF5XXX_D1_DCA(x) (((x)&0x00003000)>>12)
+#define MCF5XXX_D1_DCSIZ(x) (((x)&0x00000F00)>>8)
+#define MCF5XXX_D1_RAM1SIZ(x) (((x)&0x000000F0)>>4)
+#define MCF5XXX_D1_ROM1SIZ(x) (((x)&0x0000000F)>>0)
+
+/***********************************************************************/
+/*
+ * The ColdFire family of processors has a simplified exception stack
+ * frame that looks like the following:
+ *
+ * 3322222222221111 111111
+ * 1098765432109876 5432109876543210
+ * 8 +----------------+----------------+
+ * | Program Counter |
+ * 4 +----------------+----------------+
+ * |FS/Fmt/Vector/FS| SR |
+ * SP --> 0 +----------------+----------------+
+ *
+ * The stack self-aligns to a 4-byte boundary at an exception, with
+ * the FS/Fmt/Vector/FS field indicating the size of the adjustment
+ * (SP += 0,1,2,3 bytes).
+ */
+#define MCF5XXX_RD_SF_FORMAT(PTR) \
+ ((*((uint16 *)(PTR)) >> 12) & 0x00FF)
+
+#define MCF5XXX_RD_SF_VECTOR(PTR) \
+ ((*((uint16 *)(PTR)) >> 2) & 0x00FF)
+
+#define MCF5XXX_RD_SF_FS(PTR) \
+ ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
+
+#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
+#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
+
+/********************************************************************/
+/*
+ * Functions provided in mcf5xxx.s
+ */
+int asm_set_ipl (uint32);
+void mcf5xxx_exe_wdebug (void *);
+void mcf5xxx_wr_sr (uint32);
+void mcf5xxx_wr_cacr (uint32);
+void mcf5xxx_wr_asid (uint32);
+void mcf5xxx_wr_acr0 (uint32);
+void mcf5xxx_wr_acr1 (uint32);
+void mcf5xxx_wr_acr2 (uint32);
+void mcf5xxx_wr_acr3 (uint32);
+void mcf5xxx_wr_mmubar (uint32);
+void mcf5xxx_wr_other_a7 (uint32);
+void mcf5xxx_wr_other_sp (uint32);
+void mcf5xxx_wr_vbr (uint32);
+void mcf5xxx_wr_macsr (uint32);
+void mcf5xxx_wr_mask (uint32);
+void mcf5xxx_wr_acc0 (uint32);
+void mcf5xxx_wr_accext01 (uint32);
+void mcf5xxx_wr_accext23 (uint32);
+void mcf5xxx_wr_acc1 (uint32);
+void mcf5xxx_wr_acc2 (uint32);
+void mcf5xxx_wr_acc3 (uint32);
+void mcf5xxx_wr_pc (uint32);
+void mcf5xxx_wr_rombar0 (uint32);
+void mcf5xxx_wr_rombar1 (uint32);
+void mcf5xxx_wr_rambar0 (uint32);
+void mcf5xxx_wr_rambar1 (uint32);
+void mcf5xxx_wr_mpcr (uint32);
+void mcf5xxx_wr_secmbar (uint32);
+void mcf5xxx_wr_mbar1 (uint32);
+void mcf5xxx_wr_mbar (uint32);
+void mcf5xxx_wr_mbar0 (uint32);
+
+/*
+ * Functions provided in mcf5xxx.c
+ */
+void mcf5xxx_exception_handler (void *);
+void mcf5xxx_interpret_d0d1 (int, int);
+void mcf5xxx_irq_enable (void);
+void mcf5xxx_irq_disable (void);
+ADDRESS mcf5xxx_set_handler (int, ADDRESS);
+
+/*
+ * Functions provided by processor specific C file
+ */
+void cpu_handle_interrupt (int);
+
+/********************************************************************/
+
+#endif /* _CPU_MCF5XXX_H */
+
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/HTTPDemo.c b/Demo/ColdFire_MCF52259_CodeWarrior/HTTPDemo.c new file mode 100644 index 00000000..f92d295a --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/HTTPDemo.c @@ -0,0 +1,230 @@ +/*
+ FreeRTOS.org V5.0.3 - copyright (C) 2003-2006 Richard Barry.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ FreeRTOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with FreeRTOS; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ A special exception to the GPL can be applied should you wish to distribute
+ a combined work that includes FreeRTOS, without being obliged to provide
+ the source code for any proprietary components. See the licensing section
+ of http://www.FreeRTOS.org for full details of how and when the exception
+ can be applied.
+
+ ***************************************************************************
+ ***************************************************************************
+ * *
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
+ * and even write all or part of your application on your behalf. *
+ * See http://www.OpenRTOS.com for details of the services we provide to *
+ * expedite your project. *
+ * *
+ ***************************************************************************
+ ***************************************************************************
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+/*
+ Implements a simplistic WEB server. Every time a connection is made and
+ data is received a dynamic page that shows the current TCP/IP statistics
+ is generated and returned. The connection is then closed.
+
+ This file was adapted from a FreeRTOS lwIP slip demo supplied by a third
+ party.
+*/
+
+/* ------------------------ System includes ------------------------------- */
+
+
+/* ------------------------ FreeRTOS includes ----------------------------- */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* ------------------------ lwIP includes --------------------------------- */
+#include "lwip/api.h"
+#include "lwip/tcpip.h"
+#include "lwip/ip.h"
+#include "lwip/memp.h"
+#include "lwip/stats.h"
+#include "netif/loopif.h"
+
+/* ------------------------ Project includes ------------------------------ */
+#include "common.h"
+
+#include "HTTPDemo.h"
+
+/* ------------------------ Defines --------------------------------------- */
+/* The size of the buffer in which the dynamic WEB page is created. */
+#define webMAX_PAGE_SIZE ( 1024 ) /*FSL: buffer containing array*/
+
+/* Standard GET response. */
+#define webHTTP_OK "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n"
+
+/* The port on which we listen. */
+#define webHTTP_PORT ( 80 )
+
+/* Delay on close error. */
+#define webSHORT_DELAY ( 10 )
+
+/* Format of the dynamic page that is returned on each connection. */
+#define webHTML_START \
+"<html>\
+<head>\
+</head>\
+<BODY onLoad=\"window.setTimeout("location.href='index.html'",1000)\"bgcolor=\"#CCCCff\">\
+\r\n\r\nPage Hits = "
+
+#define webHTML_END \
+"\r\n" \
+"</pre>\r\n" \
+"</BODY>\r\n" \
+"</html>"
+
+#if INCLUDE_uxTaskGetStackHighWaterMark
+ static volatile unsigned portBASE_TYPE uxHighWaterMark_web = 0;
+#endif
+
+/* ------------------------ Prototypes ------------------------------------ */
+static void vProcessConnection( struct netconn *pxNetCon );
+
+/*------------------------------------------------------------*/
+
+/*
+ * Process an incoming connection on port 80.
+ *
+ * This simply checks to see if the incoming data contains a GET request, and
+ * if so sends back a single dynamically created page. The connection is then
+ * closed. A more complete implementation could create a task for each
+ * connection.
+ */
+static void vProcessConnection( struct netconn *pxNetCon )
+{
+ static portCHAR cDynamicPage[webMAX_PAGE_SIZE], cPageHits[11];
+ struct netbuf *pxRxBuffer;
+ portCHAR *pcRxString;
+ unsigned portSHORT usLength;
+ static unsigned portLONG ulPageHits = 0;
+
+ /* We expect to immediately get data. */
+ pxRxBuffer = netconn_recv( pxNetCon );
+
+ if( pxRxBuffer != NULL )
+ {
+ /* Where is the data? */
+ netbuf_data( pxRxBuffer, ( void * )&pcRxString, &usLength );
+
+ /* Is this a GET? We don't handle anything else. */
+ if( !strncmp( pcRxString, "GET", 3 ) )
+ {
+ pcRxString = cDynamicPage;
+
+ /* Update the hit count. */
+ ulPageHits++;
+ sprintf( cPageHits, "%d", (int)ulPageHits );
+
+ /* Write out the HTTP OK header. */
+ netconn_write( pxNetCon, webHTTP_OK, ( u16_t ) strlen( webHTTP_OK ), NETCONN_COPY );
+
+ /* Generate the dynamic page...
+
+ ... First the page header. */
+ strcpy( cDynamicPage, webHTML_START );
+ /* ... Then the hit count... */
+ strcat( cDynamicPage, cPageHits );
+
+ strcat( cDynamicPage,
+ "<p><pre>Task State Priority Stack #<br>************************************************<br>" );
+ /* ... Then the list of tasks and their status... */
+ vTaskList( ( signed portCHAR * )cDynamicPage + strlen( cDynamicPage ) );
+
+ /* ... Finally the page footer. */
+ strcat( cDynamicPage, webHTML_END );
+
+ /* Write out the dynamically generated page. */
+ netconn_write( pxNetCon, cDynamicPage, ( u16_t ) strlen( cDynamicPage ), NETCONN_COPY );
+ }
+ netbuf_delete( pxRxBuffer );
+ }
+ netconn_close( pxNetCon );
+}
+
+/*------------------------------------------------------------*/
+
+void vlwIPInit( void )
+{
+ /* Initialize lwIP and its interface layer. */
+ tcpip_init( NULL, NULL );
+}
+
+/*------------------------------------------------------------*/
+
+void vBasicWEBServer( void *pvParameters )
+{
+ struct netconn *pxHTTPListener, *pxNewConnection;
+ struct ip_addr xIpAddr, xNetMast, xGateway;
+ static struct netif fec523x_if;
+ extern err_t ethernetif_init(struct netif *netif);
+
+ /* Parameters are not used - suppress compiler error. */
+ ( void )pvParameters;
+
+ vlwIPInit();
+
+ /* Create and configure the FEC interface. */
+ IP4_ADDR( &xIpAddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 );
+ IP4_ADDR( &xNetMast, configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 );
+ IP4_ADDR( &xGateway, configGW_ADDR0, configGW_ADDR1, configGW_ADDR2, configGW_ADDR3 );
+ netif_add( &fec523x_if, &xIpAddr, &xNetMast, &xGateway, NULL, ethernetif_init, tcpip_input );
+
+ /* make it the default interface */
+ netif_set_default( &fec523x_if );
+
+ /* bring it up */
+ netif_set_up( &fec523x_if );
+
+ /* Create a new tcp connection handle */
+ pxHTTPListener = netconn_new( NETCONN_TCP );
+ netconn_bind( pxHTTPListener, NULL, webHTTP_PORT );
+ netconn_listen( pxHTTPListener );
+
+ /* Loop forever */
+ for( ;; )
+ {
+ /* Wait for connection. */
+ pxNewConnection = netconn_accept( pxHTTPListener );
+
+ if( pxNewConnection != NULL )
+ {
+ /* Service connection. */
+ vProcessConnection( pxNewConnection );
+ while( netconn_delete( pxNewConnection ) != ERR_OK )
+ {
+ vTaskDelay( webSHORT_DELAY );
+ }
+ }
+ }
+}
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/HTTPDemo.h b/Demo/ColdFire_MCF52259_CodeWarrior/HTTPDemo.h new file mode 100644 index 00000000..31ccb8ee --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/HTTPDemo.h @@ -0,0 +1,63 @@ +/*
+ FreeRTOS.org V5.0.3 - copyright (C) 2003-2006 Richard Barry.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ FreeRTOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with FreeRTOS; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ A special exception to the GPL can be applied should you wish to distribute
+ a combined work that includes FreeRTOS, without being obliged to provide
+ the source code for any proprietary components. See the licensing section
+ of http://www.FreeRTOS.org for full details of how and when the exception
+ can be applied.
+
+ ***************************************************************************
+ ***************************************************************************
+ * *
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
+ * and even write all or part of your application on your behalf. *
+ * See http://www.OpenRTOS.com for details of the services we provide to *
+ * expedite your project. *
+ * *
+ ***************************************************************************
+ ***************************************************************************
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+#ifndef BASIC_WEB_SERVER_H
+#define BASIC_WEB_SERVER_H
+
+/* The function that implements the WEB server task. */
+void vBasicWEBServer( void *pvParameters );
+
+
+/* Initialisation required by lwIP. */
+void vlwIPInit( void );
+
+
+#endif /*
+ */
+
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/ParTest/ParTest.c b/Demo/ColdFire_MCF52259_CodeWarrior/ParTest/ParTest.c new file mode 100644 index 00000000..97dfe0fb --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/ParTest/ParTest.c @@ -0,0 +1,133 @@ +/*
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.
+
+ This file is part of the FreeRTOS.org distribution.
+
+ FreeRTOS.org is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ FreeRTOS.org is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with FreeRTOS.org; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ A special exception to the GPL can be applied should you wish to distribute
+ a combined work that includes FreeRTOS.org, without being obliged to provide
+ the source code for any proprietary components. See the licensing section
+ of http://www.FreeRTOS.org for full details of how and when the exception
+ can be applied.
+
+ ***************************************************************************
+ ***************************************************************************
+ * *
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
+ * and even write all or part of your application on your behalf. *
+ * See http://www.OpenRTOS.com for details of the services we provide to *
+ * expedite your project. *
+ * *
+ ***************************************************************************
+ ***************************************************************************
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+/*
+ Changes from V2.5.2
+
+ + All LED's are turned off to start.
+*/
+
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "partest.h"
+
+#define partstNUM_LEDs 4
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines.
+ *-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+ /* Enable signals as GPIO */
+ MCF_GPIO_PTCPAR = 0
+ | MCF_GPIO_PTCPAR_DTIN3_GPIO
+ | MCF_GPIO_PTCPAR_DTIN2_GPIO
+ | MCF_GPIO_PTCPAR_DTIN1_GPIO
+ | MCF_GPIO_PTCPAR_DTIN0_GPIO;
+
+ /* Enable signals as digital outputs */
+ MCF_GPIO_DDRTC = 0
+ | MCF_GPIO_DDRTC_DDRTC3
+ | MCF_GPIO_DDRTC_DDRTC2
+ | MCF_GPIO_DDRTC_DDRTC1
+ | MCF_GPIO_DDRTC_DDRTC0;
+
+ MCF_GPIO_PORTTC = 0x00; // TURN LEDS OFF
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+unsigned portBASE_TYPE uxLEDMask;
+
+ if( uxLED < partstNUM_LEDs )
+ {
+ uxLEDMask = 1UL << uxLED;
+
+ taskENTER_CRITICAL();
+ {
+ if( xValue )
+ {
+ MCF_GPIO_PORTTC |= uxLEDMask;
+ }
+ else
+ {
+ MCF_GPIO_PORTTC &= ~uxLEDMask;
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+unsigned portBASE_TYPE uxLEDMask;
+
+ if( uxLED < partstNUM_LEDs )
+ {
+ uxLEDMask = 1UL << uxLED;
+
+ taskENTER_CRITICAL();
+ {
+ if( MCF_GPIO_PORTTC & uxLEDMask )
+ {
+ MCF_GPIO_PORTTC &= ~uxLEDMask;
+ }
+ else
+ {
+ MCF_GPIO_PORTTC |= uxLEDMask;
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+}
+
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/RTOSDemo.mcp b/Demo/ColdFire_MCF52259_CodeWarrior/RTOSDemo.mcp Binary files differnew file mode 100644 index 00000000..60936857 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/RTOSDemo.mcp diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/RTOSDemo_Data/CWSettingsWindows.stg b/Demo/ColdFire_MCF52259_CodeWarrior/RTOSDemo_Data/CWSettingsWindows.stg Binary files differnew file mode 100644 index 00000000..be222cc8 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/RTOSDemo_Data/CWSettingsWindows.stg diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/RTOSDemo_Data/INTERNAL_FLASH/TargetDataWindows.tdt b/Demo/ColdFire_MCF52259_CodeWarrior/RTOSDemo_Data/INTERNAL_FLASH/TargetDataWindows.tdt Binary files differnew file mode 100644 index 00000000..ad578b41 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/RTOSDemo_Data/INTERNAL_FLASH/TargetDataWindows.tdt diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTERNAL_FLASH.cfg b/Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTERNAL_FLASH.cfg new file mode 100644 index 00000000..b4c1de16 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTERNAL_FLASH.cfg @@ -0,0 +1,14 @@ +ResetHalt
+
+; Set VBR to the beginning of what will be SRAM
+; VBR is an absolute CPU register
+writecontrolreg 0x0801 0x20000000
+
+; Set RAMBAR1 (SRAM)
+writecontrolreg 0x0C05 0x20000021
+
+; Set FLASHBAR (Flash)
+writecontrolreg 0x0C04 0x00000061
+
+; Enable PST[3:0] signals
+writemem.b 0x40100074 0x0F
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTERNAL_FLASH.mem b/Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTERNAL_FLASH.mem new file mode 100644 index 00000000..b9db30c4 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTERNAL_FLASH.mem @@ -0,0 +1,31 @@ +// Memory Configuration File
+//
+// Description:
+// A memory configuration file contains commands that define the legally accessible
+// areas of memory for your specific board. Useful for example when the debugger
+// tries to display the content of a "char *" variable, that has not yet been initialized.
+// In this case the debugger may try to read from a bogus address, which could cause a
+// bus error.
+//
+// Board:
+// Freescale MCF52259
+//
+// Reference:
+//
+
+
+// All reserved ranges read back 0xBABA...
+reservedchar 0xBA
+
+address IPSBAR_BASE 0x40000000
+
+usederivative "MCF52259"
+
+// Memory Map:
+// ----------------------------------------------------------------------
+range 0x00000000 0x0007FFFF 4 Read // 512 KByte Internal Flash Memory
+reserved 0x00080000 0x1FFFFFFF
+range 0x20000000 0x2000FFFF 4 ReadWrite // 64 Kbytes Internal SRAM
+reserved 0x20010000 0x3FFFFFFF
+// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers
+reserved $IPSBAR_BASE + 0x200000 0xFFFFFFFF
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTFLASH.xml b/Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTFLASH.xml new file mode 100644 index 00000000..729339dd --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTFLASH.xml @@ -0,0 +1,48 @@ +<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
+
+<fpconfig xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="fp_config.xsd">
+
+ <targetconfwindow>
+ <usecustomsettings>false</usecustomsettings>
+ <targetprocessor>52259</targetprocessor>
+ <connection></connection>
+ <usetargetinit>true</usetargetinit>
+ <targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\MCF52259.cfg</targetinitfile>
+ <targetmembuffaddr>0x20000000</targetmembuffaddr>
+ <targetmembuffsize>0x00008000</targetmembuffsize>
+ <enablelogging>true</enablelogging>
+ <verifywrites>false</verifywrites>
+ </targetconfwindow>
+
+ <flashconfwindow>
+ <membaseaddr>0x00000000</membaseaddr>
+ <device>CFM_MCF5225X_512</device>
+ <organization>32Kx16x1</organization>
+ <flashstart>0x00000000</flashstart>
+ <flashend>0x0007FFFF</flashend>
+ </flashconfwindow>
+
+ <programverifywindow>
+ <useselectedfile>false</useselectedfile>
+ <projbuildtargetfile>nofile</projbuildtargetfile>
+ <fileiotype>Auto Detect</fileiotype>
+ <restrictaddrrange>false</restrictaddrrange>
+ <restrictaddrrangestart>0x00000000</restrictaddrrangestart>
+ <restrictaddrrangeend>0x0007FFFF</restrictaddrrangeend>
+ <applyaddroffset>false</applyaddroffset>
+ <addroffset>0x00000000</addroffset>
+ </programverifywindow>
+
+ <eraseblankcheckwindow>
+ <eraseallsectors>true</eraseallsectors>
+ <sector/>
+ <processsectorsindividually>false</processsectorsindividually>
+ </eraseblankcheckwindow>
+
+ <checksumwindow>
+ <computechecksumover>FileOnTarg</computechecksumover>
+ <addrstart>0x00000000</addrstart>
+ <addrsize>0x0000FFFF</addrsize>
+ </checksumwindow>
+
+</fpconfig>
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cfg/mcf5225xEVB_PnE.cfg b/Demo/ColdFire_MCF52259_CodeWarrior/cfg/mcf5225xEVB_PnE.cfg new file mode 100644 index 00000000..b4c1de16 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cfg/mcf5225xEVB_PnE.cfg @@ -0,0 +1,14 @@ +ResetHalt
+
+; Set VBR to the beginning of what will be SRAM
+; VBR is an absolute CPU register
+writecontrolreg 0x0801 0x20000000
+
+; Set RAMBAR1 (SRAM)
+writecontrolreg 0x0C05 0x20000021
+
+; Set FLASHBAR (Flash)
+writecontrolreg 0x0C04 0x00000061
+
+; Enable PST[3:0] signals
+writemem.b 0x40100074 0x0F
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x.c b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x.c new file mode 100644 index 00000000..61d82798 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x.c @@ -0,0 +1,81 @@ +/*
+ * File: mcf52xx.c
+ * Purpose: Source to select CF derivative
+ *
+ * Notes:
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+/********************************************************************/
+
+#include "common.h"
+
+/********************************************************************/
+/*
+ * Pause for the specified number of micro-seconds.
+ * Uses DTIM3 as a timer
+ */
+void
+cpu_pause(int usecs)
+{
+ /* Enable the DMA Timer 3 */
+ MCF_DTIM3_DTRR = (vuint32)(usecs - 1);
+ MCF_DTIM3_DTER = MCF_DTIM_DTER_REF;
+ MCF_DTIM3_DTMR = 0
+ | MCF_DTIM_DTMR_PS(SYSTEM_CLOCK)
+ | MCF_DTIM_DTMR_FRR
+ | MCF_DTIM_DTMR_CLK_DIV1
+ | MCF_DTIM_DTMR_RST;
+
+ while ((MCF_DTIM3_DTER & MCF_DTIM_DTER_REF) == 0)
+ {};
+
+ /* Disable the timer */
+ MCF_DTIM3_DTMR = 0;
+}
+
+/********************************************************************/
+void
+board_handle_interrupt (int vector)
+{
+ switch (vector)
+ {
+ case 65: /* Eport Interrupt 1 */
+ printf("SW2\n");
+ MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF1;
+ break;
+ case 69: /* Eport Interrupt 5 */
+ printf("SW1\n");
+ MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF5;
+ break;
+ case 71: /* Eport Interrupt 7 */
+ printf("ABORT\n");
+ MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF7;
+ break;
+ case 66: /* Eport Interrupt 2 */
+ case 67: /* Eport Interrupt 3 */
+ case 68: /* Eport Interrupt 4 */
+ case 70: /* Eport Interrupt 6 */
+ default:
+ MCF_EPORT_EPFR = (uint8)(0x01 << (vector - 64));
+ printf("Edge Port Interrupt #%d\n",vector - 64);
+ break;
+ }
+}
+/********************************************************************/
+
+/********************************************************************/
+void
+cpu_handle_interrupt (int vector)
+{
+ if (vector < 64 || vector > 192)
+ return;
+
+ if (vector >= 64 && vector <= 71)
+ board_handle_interrupt(vector);
+ else
+ printf("User Defined Vector #%d\n",vector);
+}
+/********************************************************************/
+
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x.h b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x.h new file mode 100644 index 00000000..b7225684 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x.h @@ -0,0 +1,48 @@ +/*
+ * File: mcf5225x.h
+ * Purpose: Register and bit definitions
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#ifndef __MCF5225x_H__
+#define __MCF5225x_H__
+
+/********************************************************************/
+/*
+ * 5225x includes
+ */
+
+#include "MCF52259_SCM.h"
+#include "MCF52259_DMA.h"
+#include "MCF52259_UART.h"
+#include "MCF52259_I2C.h"
+#include "MCF52259_QSPI.h"
+#include "MCF52259_TMR.h"
+#include "MCF52259_INTC.h"
+#include "MCF52259_FEC.h"
+#include "MCF52259_GPIO.h"
+#include "MCF52259_PAD.h"
+#include "MCF52259_RCM.h"
+#include "MCF52259_CCM.h"
+#include "MCF52259_PMM.h"
+#include "MCF52259_CLOCK.h"
+#include "MCF52259_EPORT.h"
+#include "MCF52259_BWT.h"
+#include "MCF52259_PIT.h"
+#include "MCF52259_FlexCAN.h"
+#include "MCF52259_RTC.h"
+#include "MCF52259_ADC.h"
+#include "MCF52259_GPT.h"
+#include "MCF52259_PWM.h"
+#include "MCF52259_USB_OTG.h"
+#include "MCF52259_CFM.h"
+#include "MCF52259_RNGA.h"
+#include "MCF52259_fbcs.h"
+#include "mcf52259_dtim.h"
+
+
+/********************************************************************/
+
+#endif /* __MCF5225x_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_lo.s b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_lo.s new file mode 100644 index 00000000..4fc6b89e --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_lo.s @@ -0,0 +1,153 @@ +/*
+ * File: mcf5225x_lo.s
+ * Purpose: Low-level routines for the MCF5225x.
+ *
+ * Notes:
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#define mcf5225x_init _mcf5225x_init
+#define common_startup _common_startup
+#define cpu_startup _cpu_startup
+#define main _main
+#define __IPSBAR ___IPSBAR
+#define __SRAM ___SRAM
+#define __FLASH ___FLASH
+#define __SP_INIT ___SP_INIT
+
+ .extern __IPSBAR
+ .extern __SRAM
+ .extern __FLASH
+ .extern __SP_INIT
+ .extern mcf5225x_init
+ .extern common_startup
+ .extern cpu_startup
+ .extern main
+
+ .global asm_startmeup
+ .global _asm_startmeup
+ .global d0_reset
+ .global _d0_reset
+ .global d1_reset
+ .global _d1_reset
+
+ .data
+
+d0_reset:
+_d0_reset: .long 0
+d1_reset:
+_d1_reset: .long 0
+
+ .text
+
+/********************************************************************
+ *
+ * This is the main entry point upon hard reset. The memory map is
+ * setup based on linker file definitions, then the higher level
+ * system initialization routine is called. Finally, we jump to the
+ * "main" process.
+ */
+asm_startmeup:
+_asm_startmeup:
+
+ move.w #0x2700,sr
+
+ /* Save off reset values of D0 and D1 */
+ move.l d0,d6
+ move.l d1,d7
+
+ /* Initialize RAMBAR1: locate SRAM and validate it */
+ move.l #__SRAM,d0
+ andi.l #0xFFFF0000,d0
+ add.l #0x21,d0
+ movec d0,RAMBAR1
+
+ /* Locate Stack Pointer */
+ move.l #__SP_INIT,sp
+
+ /* Initialize IPSBAR */
+ move.l #__IPSBAR,d0
+ add.l #0x1,d0
+ move.l d0,0x40000000
+
+ /* Initialize FLASHBAR */
+ move.l #__FLASH,d0
+ cmp.l #0x00000000,d0
+ bne change_flashbar
+ add.l #0x61,d0
+ movec d0,RAMBAR0
+
+_continue_startup:
+
+ /* Locate Stack Pointer */
+ move.l #__SP_INIT,sp
+
+ /* Initialize the system */
+ jsr mcf5225x_init
+
+ /* Common startup code */
+ //jsr common_startup
+
+ /* Save off intial D0 and D1 to RAM */
+ move.l d6,d0_reset
+ move.l d7,d1_reset
+
+ /* CPU specific startup code */
+ //jsr cpu_startup
+
+ /* Jump to the main process */
+ jsr main
+
+ bra .
+ nop
+ nop
+ halt
+
+change_flashbar:
+ /*
+ * The following sequence is used to set FLASHBAR. Since we may
+ * be executing from Flash, we must put the routine into SRAM for
+ * execution and then jump back to Flash using the new address.
+ *
+ * The following instructions are coded into the SRAM:
+ *
+ * move.l #(__FLASH + 0x21),d0
+ * movec d0, RAMBAR0
+ * jmp _continue_startup
+ *
+ * An arbitrary SRAM address is chosen until the real address
+ * can be loaded.
+ *
+ * This routine is not necessary if the default Flash address
+ * (0x00000000) is used.
+ *
+ * If running in SRAM, change_flashbar should not be executed
+ */
+
+ move.l #__SRAM,a0
+
+ /* Code "move.l #(__FLASH + 0x21),d0" into SRAM */
+ move.w #0x203C,d0
+ move.w d0,(a0)+
+ move.l #__FLASH,d0
+ add.l #0x21,d0
+ move.l d0,(a0)+
+
+ /* Code "movec d0,FLASHBAR" into SRAM */
+ move.l #0x4e7b0C04,d0
+ move.l d0,(a0)+
+
+ /* Code "jmp _continue_startup" into SRAM */
+ move.w #0x4EF9,d0
+ move.w d0,(a0)+
+ move.l #_continue_startup,d0
+ move.l d0,(a0)+
+
+ /* Jump to code segment in internal SRAM */
+ jmp __SRAM
+
+/********************************************************************/
+
+ .end
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_sysinit.c b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_sysinit.c new file mode 100644 index 00000000..8dc8a97b --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_sysinit.c @@ -0,0 +1,301 @@ +/*
+ * File: sysinit.c
+ * Purpose: Reset configuration of the M52259EVB
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#include "common.h"
+
+/********************************************************************/
+
+void mcf5225x_init(void);
+void mcf5225x_wtm_init(void);
+void mcf5225x_pll_init(void);
+void mcf5225x_uart_init(void);
+void mcf5225x_scm_init(void);
+void mcf5225x_gpio_init(void);
+
+/********************************************************************/
+void
+mcf5225x_init(void)
+{
+ register uint32 n;
+ register uint8 *dp, *sp;
+
+
+ /*
+ * Allow interrupts from ABORT, SW1, SW2 (IRQ[1,5,7])
+ * and USB (IRQ[2,6])
+ */
+
+
+ /* Enable IRQ signals on the port */
+ MCF_GPIO_PNQPAR = 0
+ | MCF_GPIO_PNQPAR_IRQ1_IRQ1
+ | MCF_GPIO_PNQPAR_IRQ5_IRQ5
+ | MCF_GPIO_PNQPAR_IRQ7_IRQ7;
+
+ /* Set EPORT to look for falling edges */
+ MCF_EPORT_EPPAR = 0
+ | MCF_EPORT_EPPAR_EPPA1_FALLING
+ | MCF_EPORT_EPPAR_EPPA2_FALLING
+ | MCF_EPORT_EPPAR_EPPA5_FALLING
+ | MCF_EPORT_EPPAR_EPPA6_FALLING
+ | MCF_EPORT_EPPAR_EPPA7_FALLING;
+
+ /* Clear any currently triggered events on the EPORT */
+ MCF_EPORT_EPIER = 0
+ | MCF_EPORT_EPIER_EPIE1
+ | MCF_EPORT_EPIER_EPIE2
+ | MCF_EPORT_EPIER_EPIE5
+ | MCF_EPORT_EPIER_EPIE6
+ | MCF_EPORT_EPIER_EPIE7;
+
+ /* Enable interrupts in the interrupt controller */
+ MCF_INTC0_IMRL &= ~(0
+ | MCF_INTC_IMRL_INT_MASK1
+ | MCF_INTC_IMRL_INT_MASK2
+ | MCF_INTC_IMRL_INT_MASK5
+ | MCF_INTC_IMRL_INT_MASK6
+ | MCF_INTC_IMRL_INT_MASK7
+ | MCF_INTC_IMRL_MASKALL);
+
+
+ /* Enable debug */
+ MCF_GPIO_PDDPAR = 0x0F;
+
+ /* Set real time clock freq */
+
+ MCF_CLOCK_RTCCR = 48000000;
+
+ /* Copy the vector table to RAM */
+ if (__VECTOR_RAM != VECTOR_TABLE)
+ {
+ for (n = 0; n < 256; n++)
+ __VECTOR_RAM[n] = VECTOR_TABLE[n];
+
+ mcf5xxx_wr_vbr((uint32)__VECTOR_RAM);
+ }
+
+ /*
+ * Move initialized data from ROM to RAM.
+ */
+ if (__DATA_ROM != __DATA_RAM)
+ {
+ dp = (uint8 *)__DATA_RAM;
+ sp = (uint8 *)__DATA_ROM;
+ n = (uint32)(__DATA_END - __DATA_RAM);
+ while (n--)
+ *dp++ = *sp++;
+ }
+
+ /*
+ * Zero uninitialized data
+ */
+ if (__BSS_START != __BSS_END)
+ {
+ sp = (uint8 *)__BSS_START;
+ n = (uint32)(__BSS_END - __BSS_START);
+ while (n--)
+ *sp++ = 0;
+ }
+ mcf5225x_wtm_init();
+
+ mcf5225x_pll_init();
+ mcf5225x_scm_init();
+ mcf5225x_uart_init();
+}
+/********************************************************************/
+void
+mcf5225x_wtm_init(void)
+{
+ /*
+ * Disable Software Watchdog Timer
+ */
+ MCF_SCM_CWCR = 0;
+}
+/********************************************************************/
+void
+mcf5225x_pll_init(void)
+{
+ /*Required if booting with internal relaxation oscillator & pll off, clkmod[1:0]=00 & xtal=1 */
+#ifndef OMIT_OCLR_CONFIGURATION
+ MCF_CLOCK_OCLR = 0xC0; //turn on crystal
+ MCF_CLOCK_CCLR = 0x00; //switch to crystal
+ MCF_CLOCK_OCHR = 0x00; //turn off relaxation osc
+#endif
+
+ /* The PLL pre divider - 48MHz / 6 = 8MHz */
+ MCF_CLOCK_CCHR =0x05;
+
+
+ /* The PLL pre-divider affects this!!!
+ * Multiply 48Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz
+ */
+
+ MCF_CLOCK_SYNCR &= ~(MCF_CLOCK_SYNCR_PLLEN);
+
+ MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_CLKSRC | MCF_CLOCK_SYNCR_PLLMODE;
+
+ //80
+ MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_RFD(0);
+ //64
+ //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(0);
+ //16
+ //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(2);
+ //8
+ //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(3);
+ //1
+ //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(6);
+
+ MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_PLLEN;
+
+
+ while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
+ {
+ }
+}
+/********************************************************************/
+void
+mcf5225x_scm_init(void)
+{
+ /*
+ * Enable on-chip modules to access internal SRAM
+ */
+ MCF_SCM_RAMBAR = (0
+ | MCF_SCM_RAMBAR_BA(SRAM_ADDRESS)
+ | MCF_SCM_RAMBAR_BDE);
+}
+/********************************************************************/
+void
+mcf5225x_gpio_init(void)
+{
+ /*
+ * Initialize Port TA to enable Axcel control
+ */
+ MCF_GPIO_PTAPAR = 0x00;
+ MCF_GPIO_DDRTA = 0x0F;
+ MCF_GPIO_PORTTA = 0x04;
+
+}
+/********************************************************************/
+void
+mcf5225x_uart_init(void)
+{
+ /*
+ * Initialize all three UARTs for serial communications
+ */
+
+ register uint16 ubgs;
+
+ /*
+ * Set Port UA to initialize URXD0/UTXD0
+ */
+ MCF_GPIO_PUAPAR = 0
+ | MCF_GPIO_PUAPAR_URXD0_URXD0
+ | MCF_GPIO_PUAPAR_UTXD0_UTXD0;
+
+ MCF_GPIO_PUBPAR = 0
+ | MCF_GPIO_PUBPAR_URXD1_URXD1
+ | MCF_GPIO_PUBPAR_UTXD1_UTXD1;
+
+ MCF_GPIO_PUCPAR = 0
+ | MCF_GPIO_PUCPAR_URXD2_URXD2
+ | MCF_GPIO_PUCPAR_UTXD2_UTXD2;
+
+ /*
+ * Reset Transmitter
+ */
+ MCF_UART0_UCR = MCF_UART_UCR_RESET_TX;
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_TX;
+ MCF_UART2_UCR = MCF_UART_UCR_RESET_TX;
+
+ /*
+ * Reset Receiver
+ */
+ MCF_UART0_UCR = MCF_UART_UCR_RESET_RX;
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_RX;
+ MCF_UART2_UCR = MCF_UART_UCR_RESET_RX;
+
+ /*
+ * Reset Mode Register
+ */
+ MCF_UART0_UCR = MCF_UART_UCR_RESET_MR;
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_MR;
+ MCF_UART2_UCR = MCF_UART_UCR_RESET_MR;
+
+ /*
+ * No parity, 8-bits per character
+ */
+ MCF_UART0_UMR1 = (0
+ | MCF_UART_UMR_PM_NONE
+ | MCF_UART_UMR_BC_8 );
+ MCF_UART1_UMR1 = (0
+ | MCF_UART_UMR_PM_NONE
+ | MCF_UART_UMR_BC_8 );
+ MCF_UART2_UMR1 = (0
+ | MCF_UART_UMR_PM_NONE
+ | MCF_UART_UMR_BC_8 );
+
+ /*
+ * No echo or loopback, 1 stop bit
+ */
+ MCF_UART0_UMR2 = (0
+ | MCF_UART_UMR_CM_NORMAL
+ | MCF_UART_UMR_SB_STOP_BITS_1);
+ MCF_UART1_UMR2 = (0
+ | MCF_UART_UMR_CM_NORMAL
+ | MCF_UART_UMR_SB_STOP_BITS_1);
+ MCF_UART2_UMR2 = (0
+ | MCF_UART_UMR_CM_NORMAL
+ | MCF_UART_UMR_SB_STOP_BITS_1);
+
+ /*
+ * Set Rx and Tx baud by SYSTEM CLOCK
+ */
+ MCF_UART0_UCSR = (0
+ | MCF_UART_UCSR_RCS_SYS_CLK
+ | MCF_UART_UCSR_TCS_SYS_CLK);
+ MCF_UART1_UCSR = (0
+ | MCF_UART_UCSR_RCS_SYS_CLK
+ | MCF_UART_UCSR_TCS_SYS_CLK);
+ MCF_UART2_UCSR = (0
+ | MCF_UART_UCSR_RCS_SYS_CLK
+ | MCF_UART_UCSR_TCS_SYS_CLK);
+
+ /*
+ * Mask all UART interrupts
+ */
+ MCF_UART0_UIMR = 0;
+ MCF_UART1_UIMR = 0;
+ MCF_UART2_UIMR = 0;
+
+ /*
+ * Calculate baud settings
+ */
+ ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(UART_BAUD * 32));
+
+ MCF_UART0_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
+ MCF_UART0_UBG2 = (uint8)(ubgs & 0x00FF);
+ MCF_UART1_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
+ MCF_UART1_UBG2 = (uint8)(ubgs & 0x00FF);
+ MCF_UART2_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
+ MCF_UART2_UBG2 = (uint8)(ubgs & 0x00FF);
+
+ /*
+ * Enable receiver and transmitter
+ */
+ MCF_UART0_UCR = (0
+ | MCF_UART_UCR_TX_ENABLED
+ | MCF_UART_UCR_RX_ENABLED);
+ MCF_UART1_UCR = (0
+ | MCF_UART_UCR_TX_ENABLED
+ | MCF_UART_UCR_RX_ENABLED);
+ MCF_UART2_UCR = (0
+ | MCF_UART_UCR_TX_ENABLED
+ | MCF_UART_UCR_RX_ENABLED);
+
+}
+/********************************************************************/
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_vectors.s b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_vectors.s new file mode 100644 index 00000000..830c8b55 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_vectors.s @@ -0,0 +1,242 @@ +/*
+ * File: vectors.s
+ * Purpose: MCF5225x vector table
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#ifdef __GNUC__ /* { */
+#define sr %sr
+#define _asm_exception_handler irq_handler
+#define _timer_handler timer_handler
+#endif /* } __GNUC__ */
+
+ .global VECTOR_TABLE
+ .global _VECTOR_TABLE
+ .global start
+
+ .extern ___SP_INIT
+ .extern _asm_startmeup
+ .extern _asm_exception_handler
+ .extern _vPIT0InterruptHandler
+ .extern vPortYieldISR
+ .extern _vFECISRHandler
+ .text
+
+/*
+ * Exception Vector Table
+ */
+VECTOR_TABLE:
+_VECTOR_TABLE:
+INITSP: .long ___SP_INIT /* Initial SP */
+INITPC: .long _asm_startmeup /* Initial PC */
+vector02: .long _asm_exception_handler /* Access Error */
+vector03: .long _asm_exception_handler /* Address Error */
+vector04: .long _asm_exception_handler /* Illegal Instruction */
+vector05: .long _asm_exception_handler /* Reserved */
+vector06: .long _asm_exception_handler /* Reserved */
+vector07: .long _asm_exception_handler /* Reserved */
+vector08: .long _asm_exception_handler /* Privilege Violation */
+vector09: .long _asm_exception_handler /* Trace */
+vector0A: .long _asm_exception_handler /* Unimplemented A-Line */
+vector0B: .long _asm_exception_handler /* Unimplemented F-Line */
+vector0C: .long _asm_exception_handler /* Debug Interrupt */
+vector0D: .long _asm_exception_handler /* Reserved */
+vector0E: .long _asm_exception_handler /* Format Error */
+vector0F: .long _asm_exception_handler /* Unitialized Int. */
+vector10: .long _asm_exception_handler /* Reserved */
+vector11: .long _asm_exception_handler /* Reserved */
+vector12: .long _asm_exception_handler /* Reserved */
+vector13: .long _asm_exception_handler /* Reserved */
+vector14: .long _asm_exception_handler /* Reserved */
+vector15: .long _asm_exception_handler /* Reserved */
+vector16: .long _asm_exception_handler /* Reserved */
+vector17: .long _asm_exception_handler /* Reserved */
+vector18: .long _asm_exception_handler /* Spurious Interrupt */
+vector19: .long _asm_exception_handler /* Autovector Level 1 */
+vector1A: .long _asm_exception_handler /* Autovector Level 2 */
+vector1B: .long _asm_exception_handler /* Autovector Level 3 */
+vector1C: .long _asm_exception_handler /* Autovector Level 4 */
+vector1D: .long _asm_exception_handler /* Autovector Level 5 */
+vector1E: .long _asm_exception_handler /* Autovector Level 6 */
+vector1F: .long _asm_exception_handler /* Autovector Level 7 */
+vector20: .long _asm_exception_handler /* TRAP #0 */
+vector21: .long _asm_exception_handler /* TRAP #1 */
+vector22: .long _asm_exception_handler /* TRAP #2 */
+vector23: .long _asm_exception_handler /* TRAP #3 */
+vector24: .long _asm_exception_handler /* TRAP #4 */
+vector25: .long _asm_exception_handler /* TRAP #5 */
+vector26: .long _asm_exception_handler /* TRAP #6 */
+vector27: .long _asm_exception_handler /* TRAP #7 */
+vector28: .long _asm_exception_handler /* TRAP #8 */
+vector29: .long _asm_exception_handler /* TRAP #9 */
+vector2A: .long _asm_exception_handler /* TRAP #10 */
+vector2B: .long _asm_exception_handler /* TRAP #11 */
+vector2C: .long _asm_exception_handler /* TRAP #12 */
+vector2D: .long _asm_exception_handler /* TRAP #13 */
+vector2E: .long _asm_exception_handler /* TRAP #14 */
+vector2F: .long _asm_exception_handler /* TRAP #15 */
+vector30: .long _asm_exception_handler /* Reserved */
+vector31: .long _asm_exception_handler /* Reserved */
+vector32: .long _asm_exception_handler /* Reserved */
+vector33: .long _asm_exception_handler /* Reserved */
+vector34: .long _asm_exception_handler /* Reserved */
+vector35: .long _asm_exception_handler /* Reserved */
+vector36: .long _asm_exception_handler /* Reserved */
+vector37: .long _asm_exception_handler /* Reserved */
+vector38: .long _asm_exception_handler /* Reserved */
+vector39: .long _asm_exception_handler /* Reserved */
+vector3A: .long _asm_exception_handler /* Reserved */
+vector3B: .long _asm_exception_handler /* Reserved */
+vector3C: .long _asm_exception_handler /* Reserved */
+vector3D: .long _asm_exception_handler /* Reserved */
+vector3E: .long _asm_exception_handler /* Reserved */
+vector3F: .long _asm_exception_handler /* Reserved */
+vector40: .long _asm_exception_handler
+vector41: .long _asm_exception_handler
+vector42: .long _asm_exception_handler
+vector43: .long _asm_exception_handler
+vector44: .long _asm_exception_handler
+vector45: .long _asm_exception_handler
+vector46: .long _asm_exception_handler
+vector47: .long _asm_exception_handler
+vector48: .long _asm_exception_handler
+vector49: .long _asm_exception_handler
+vector4A: .long _asm_exception_handler
+vector4B: .long _asm_exception_handler
+vector4C: .long _asm_exception_handler
+vector4D: .long _asm_exception_handler
+vector4E: .long _asm_exception_handler
+vector4F: .long _asm_exception_handler
+vector50: .long vPortYieldISR
+vector51: .long _asm_exception_handler
+vector52: .long _asm_exception_handler
+vector53: .long _asm_exception_handler
+vector54: .long _asm_exception_handler
+vector55: .long _asm_exception_handler
+vector56: .long _asm_exception_handler
+vector57: .long _asm_exception_handler
+vector58: .long _asm_exception_handler
+vector59: .long _vFECISRHandler
+vector5A: .long _vFECISRHandler
+vector5B: .long _vFECISRHandler
+vector5C: .long _vFECISRHandler
+vector5D: .long _vFECISRHandler
+vector5E: .long _vFECISRHandler
+vector5F: .long _vFECISRHandler
+vector60: .long _asm_exception_handler
+vector61: .long _vFECISRHandler
+vector62: .long _vFECISRHandler
+vector63: .long _vFECISRHandler
+vector64: .long _asm_exception_handler
+vector65: .long _asm_exception_handler
+vector66: .long _asm_exception_handler
+vector67: .long _asm_exception_handler
+vector68: .long _asm_exception_handler
+vector69: .long _asm_exception_handler
+vector6A: .long _asm_exception_handler
+vector6B: .long _asm_exception_handler
+vector6C: .long _asm_exception_handler
+vector6D: .long _asm_exception_handler
+vector6E: .long _asm_exception_handler
+vector6F: .long _asm_exception_handler
+vector70: .long _asm_exception_handler
+vector71: .long _asm_exception_handler
+vector72: .long _asm_exception_handler
+vector73: .long _asm_exception_handler
+vector74: .long _asm_exception_handler
+vector75: .long _asm_exception_handler
+vector76: .long _asm_exception_handler
+vector77: .long _vPIT0InterruptHandler
+vector78: .long _asm_exception_handler
+vector79: .long _asm_exception_handler
+vector7A: .long _asm_exception_handler
+vector7B: .long _asm_exception_handler
+vector7C: .long _asm_exception_handler
+vector7D: .long _asm_exception_handler
+vector7E: .long _asm_exception_handler
+vector7F: .long _asm_exception_handler
+vector80: .long _asm_exception_handler
+vector81: .long _asm_exception_handler
+vector82: .long _asm_exception_handler
+vector83: .long _asm_exception_handler
+vector84: .long _asm_exception_handler
+vector85: .long _asm_exception_handler
+vector86: .long _asm_exception_handler
+vector87: .long _asm_exception_handler
+vector88: .long _asm_exception_handler
+vector89: .long _asm_exception_handler
+vector8A: .long _asm_exception_handler
+vector8B: .long _asm_exception_handler
+vector8C: .long _asm_exception_handler
+vector8D: .long _asm_exception_handler
+vector8E: .long _asm_exception_handler
+vector8F: .long _asm_exception_handler
+vector90: .long _asm_exception_handler
+vector91: .long _asm_exception_handler
+vector92: .long _asm_exception_handler
+vector93: .long _asm_exception_handler
+vector94: .long _asm_exception_handler
+vector95: .long _asm_exception_handler
+vector96: .long _asm_exception_handler
+vector97: .long _asm_exception_handler
+vector98: .long _asm_exception_handler
+vector99: .long _asm_exception_handler
+vector9A: .long _asm_exception_handler
+vector9B: .long _asm_exception_handler
+vector9C: .long _asm_exception_handler
+vector9D: .long _asm_exception_handler
+vector9E: .long _asm_exception_handler
+vector9F: .long _asm_exception_handler
+vectorA0: .long _asm_exception_handler
+vectorA1: .long _asm_exception_handler
+vectorA2: .long _asm_exception_handler
+vectorA3: .long _asm_exception_handler
+vectorA4: .long _asm_exception_handler
+vectorA5: .long _asm_exception_handler
+vectorA6: .long _asm_exception_handler
+vectorA7: .long _asm_exception_handler
+vectorA8: .long _asm_exception_handler
+vectorA9: .long _asm_exception_handler
+vectorAA: .long _asm_exception_handler
+vectorAB: .long _asm_exception_handler
+vectorAC: .long _asm_exception_handler
+vectorAD: .long _asm_exception_handler
+vectorAE: .long _asm_exception_handler
+vectorAF: .long _asm_exception_handler
+vectorB0: .long _asm_exception_handler
+vectorB1: .long _asm_exception_handler
+vectorB2: .long _asm_exception_handler
+vectorB3: .long _asm_exception_handler
+vectorB4: .long _asm_exception_handler
+vectorB5: .long _asm_exception_handler
+vectorB6: .long _asm_exception_handler
+vectorB7: .long _asm_exception_handler
+vectorB8: .long _asm_exception_handler
+vectorB9: .long _asm_exception_handler
+vectorBA: .long _asm_exception_handler
+vectorBB: .long _asm_exception_handler
+vectorBC: .long _asm_exception_handler
+vectorBD: .long _asm_exception_handler
+vectorBE: .long _asm_exception_handler
+vectorBF: .long _asm_exception_handler
+
+ .org 0x400
+
+/*
+ * CFM Flash Configuration Field
+ */
+KEY_UPPER: .long 0x00000000
+KEY_LOWER: .long 0x00000000
+CFMPROT: .long 0x00000000
+CFMSACC: .long 0x00000000
+CFMDACC: .long 0x00000000
+CFMSEC: .long 0x00000000
+
+
+/********************************************************************/
+
+
+
+ .end
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5xxx.c b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5xxx.c new file mode 100644 index 00000000..1f2a4f21 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5xxx.c @@ -0,0 +1,516 @@ +/*
+ * File: mcf5xxx.c
+ * Purpose: Generic high-level routines for generic ColdFire processors
+ *
+ * Notes:
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#include "common.h"
+
+/********************************************************************/
+
+#define EXCEPTFMT "%s -- PC = %#08X\n"
+
+/********************************************************************/
+/*
+ * This is the exception handler for all defined exceptions. Most
+ * exceptions do nothing, but some of the more important ones are
+ * handled to some extent.
+ *
+ * Called by asm_exception_handler
+ */
+void
+mcf5xxx_exception_handler (void *framep)
+{
+ switch (MCF5XXX_RD_SF_FORMAT(framep))
+ {
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ break;
+ default:
+ printf(EXCEPTFMT,"Illegal stack type", MCF5XXX_SF_PC(framep));
+ break;
+ }
+
+ switch (MCF5XXX_RD_SF_VECTOR(framep))
+ {
+ case 2:
+ printf(EXCEPTFMT, "Access Error", MCF5XXX_SF_PC(framep));
+ switch (MCF5XXX_RD_SF_FS(framep))
+ {
+ case 4:
+ printf("Error on instruction fetch\n");
+ break;
+ case 8:
+ printf("Error on operand write\n");
+ break;
+ case 9:
+ printf("Attempted write to write-protected space\n");
+ break;
+ case 12:
+ printf("Error on operand read\n");
+ break;
+ default:
+ printf("Reserved Fault Status Encoding\n");
+ break;
+ }
+ break;
+ case 3:
+ printf(EXCEPTFMT, "Address Error", MCF5XXX_SF_PC(framep));
+ switch (MCF5XXX_RD_SF_FS(framep))
+ {
+ case 4:
+ printf("Error on instruction fetch\n");
+ break;
+ case 8:
+ printf("Error on operand write\n");
+ break;
+ case 9:
+ printf("Attempted write to write-protected space\n");
+ break;
+ case 12:
+ printf("Error on operand read\n");
+ break;
+ default:
+ printf("Reserved Fault Status Encoding\n");
+ break;
+ }
+ break;
+ case 4:
+ printf(EXCEPTFMT, "Illegal instruction", MCF5XXX_SF_PC(framep));
+ break;
+ case 8:
+ printf(EXCEPTFMT, "Privilege violation", MCF5XXX_SF_PC(framep));
+ break;
+ case 9:
+ printf(EXCEPTFMT, "Trace Exception", MCF5XXX_SF_PC(framep));
+ break;
+ case 10:
+ printf(EXCEPTFMT, "Unimplemented A-Line Instruction", \
+ MCF5XXX_SF_PC(framep));
+ break;
+ case 11:
+ printf(EXCEPTFMT, "Unimplemented F-Line Instruction", \
+ MCF5XXX_SF_PC(framep));
+ break;
+ case 12:
+ printf(EXCEPTFMT, "Debug Interrupt", MCF5XXX_SF_PC(framep));
+ break;
+ case 14:
+ printf(EXCEPTFMT, "Format Error", MCF5XXX_SF_PC(framep));
+ break;
+ case 15:
+ printf(EXCEPTFMT, "Unitialized Interrupt", MCF5XXX_SF_PC(framep));
+ break;
+ case 24:
+ printf(EXCEPTFMT, "Spurious Interrupt", MCF5XXX_SF_PC(framep));
+ break;
+ case 25:
+ case 26:
+ case 27:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ printf("Autovector interrupt level %d\n",
+ MCF5XXX_RD_SF_VECTOR(framep) - 24);
+ break;
+ case 32:
+ case 33:
+ case 34:
+ case 35:
+ case 36:
+ case 37:
+ case 38:
+ case 39:
+ case 40:
+ case 41:
+ case 42:
+ case 43:
+ case 44:
+ case 45:
+ case 46:
+ case 47:
+ printf("TRAP #%d\n", MCF5XXX_RD_SF_VECTOR(framep) - 32);
+ break;
+ case 5:
+ case 6:
+ case 7:
+ case 13:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 48:
+ case 49:
+ case 50:
+ case 51:
+ case 52:
+ case 53:
+ case 54:
+ case 55:
+ case 56:
+ case 57:
+ case 58:
+ case 59:
+ case 60:
+ case 61:
+ case 62:
+ case 63:
+ printf("Reserved: #%d\n", MCF5XXX_RD_SF_VECTOR(framep));
+ break;
+ default:
+ cpu_handle_interrupt(MCF5XXX_RD_SF_VECTOR(framep));
+ break;
+ }
+}
+
+/********************************************************************/
+/*
+ * Interpret the reset values of D0 and D1
+ *
+ * Parameters:
+ * d0 - the reset value of data register zero
+ * d1 - the reset value of data register one
+ */
+void
+mcf5xxx_interpret_d0d1(int d0, int d1)
+{
+#ifdef DEBUG_PRINT
+ printf("\nColdFire Core Configuration:\n");
+ printf("----------------------------\n");
+ printf("Processor Family %#02x\n",MCF5XXX_D0_PF(d0));
+ printf("ColdFire Core Version: %d\n",MCF5XXX_D0_VER(d0));
+ printf("Processor Revision: %d\n",MCF5XXX_D0_REV(d1));
+ printf("Bus Width: ");
+ switch (MCF5XXX_D1_BUSW(d1))
+ {
+ case 0:
+ printf("32-bit\n");
+ break;
+ default:
+ printf("Reserved\n");
+ }
+ printf("ISA Version: ");
+ switch (MCF5XXX_D0_ISA(d0))
+ {
+ case 0:
+ printf("A\n");
+ break;
+ case 1:
+ printf("B\n");
+ break;
+ case 2:
+ printf("C\n");
+ break;
+ case 8:
+ printf("A+\n");
+ break;
+ default:
+ printf("Reserved\n");
+ }
+ printf("Debug Version: ");
+ switch (MCF5XXX_D0_DEBUG(d0))
+ {
+ case 0:
+ printf("A\n");
+ break;
+ case 1:
+ printf("B\n");
+ break;
+ case 2:
+ printf("C\n");
+ break;
+ case 3:
+ printf("D\n");
+ break;
+ case 4:
+ printf("E\n");
+ break;
+ case 9:
+ printf("B+\n");
+ break;
+ default :
+ printf("Reserved\n");
+ }
+ printf("MAC: %s\n", MCF5XXX_D0_MAC(d0) ? "Yes" : "No");
+ printf("DIV: %s\n", MCF5XXX_D0_DIV(d0) ? "Yes" : "No");
+ printf("EMAC: %s\n", MCF5XXX_D0_EMAC(d0) ? "Yes" : "No");
+ printf("FPU: %s\n", MCF5XXX_D0_FPU(d0) ? "Yes" : "No");
+ printf("MMU: %s\n", MCF5XXX_D0_MMU(d0) ? "Yes" : "No");
+ printf("RAM Bank 0 Size: ");
+ switch (MCF5XXX_D1_RAM0SIZ(d1))
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ printf("None\n");
+ break;
+ case 4:
+ printf("4KB\n");
+ break;
+ case 5:
+ printf("8KB\n");
+ break;
+ case 6:
+ printf("16KB\n");
+ break;
+ case 7:
+ printf("32KB\n");
+ break;
+ case 8:
+ printf("64KB\n");
+ break;
+ case 9:
+ printf("128KB\n");
+ break;
+ case 10:
+ printf("256KB\n");
+ break;
+ case 11:
+ printf("512KB\n");
+ break;
+ default:
+ printf("Reserved\n");
+ }
+ printf("RAM Bank 1 Size: ");
+ switch (MCF5XXX_D1_RAM1SIZ(d1))
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ printf("None\n");
+ break;
+ case 4:
+ printf("4KB\n");
+ break;
+ case 5:
+ printf("8KB\n");
+ break;
+ case 6:
+ printf("16KB\n");
+ break;
+ case 7:
+ printf("32KB\n");
+ break;
+ case 8:
+ printf("64KB\n");
+ break;
+ case 9:
+ printf("128KB\n");
+ break;
+ case 10:
+ printf("256KB\n");
+ break;
+ case 11:
+ printf("512KB\n");
+ break;
+ default:
+ printf("Reserved\n");
+ }
+ printf("ROM Bank 0 Size: ");
+ switch (MCF5XXX_D1_ROM0SIZ(d1))
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ printf("None\n");
+ break;
+ case 4:
+ printf("4KB\n");
+ break;
+ case 5:
+ printf("8KB\n");
+ break;
+ case 6:
+ printf("16KB\n");
+ break;
+ case 7:
+ printf("32KB\n");
+ break;
+ case 8:
+ printf("64KB\n");
+ break;
+ case 9:
+ printf("128KB\n");
+ default:
+ printf("Reserved\n");
+ }
+ printf("ROM Bank 1 Size: ");
+ switch (MCF5XXX_D1_ROM1SIZ(d1))
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ printf("None\n");
+ break;
+ case 4:
+ printf("4KB\n");
+ break;
+ case 5:
+ printf("8KB\n");
+ break;
+ case 6:
+ printf("16KB\n");
+ break;
+ case 7:
+ printf("32KB\n");
+ break;
+ case 8:
+ printf("64KB\n");
+ break;
+ case 9:
+ printf("128KB\n");
+ default:
+ printf("Reserved\n");
+ }
+ printf("Cache Line Size: ");
+ switch (MCF5XXX_D1_CL(d1))
+ {
+ case 0:
+ printf("16-byte\n");
+ break;
+ default:
+ printf("Reserved\n");
+ }
+ printf("I-Cache Associativity: ");
+ switch (MCF5XXX_D1_ICA(d1))
+ {
+ case 0:
+ printf("Four-way\n");
+ break;
+ case 1:
+ printf("Direct mapped\n");
+ break;
+ default:
+ printf("Reserved\n");
+ }
+ printf("D-Cache Associativity: ");
+ switch (MCF5XXX_D1_DCA(d1))
+ {
+ case 0:
+ printf("Four-way\n");
+ break;
+ case 1:
+ printf("Direct mapped\n");
+ break;
+ default:
+ printf("Reserved\n");
+ }
+ printf("I-Cache Size: ");
+ switch (MCF5XXX_D1_ICSIZ(d1))
+ {
+ case 0:
+ printf("None\n");
+ break;
+ case 1:
+ printf("512B\n");
+ break;
+ case 2:
+ printf("1KB\n");
+ break;
+ case 3:
+ printf("2KB\n");
+ break;
+ case 4:
+ printf("4KB\n");
+ break;
+ case 5:
+ printf("8KB\n");
+ break;
+ case 6:
+ printf("16KB\n");
+ break;
+ case 7:
+ printf("32KB\n");
+ break;
+ case 8:
+ printf("64KB\n");
+ break;
+ default:
+ printf("Reserved\n");
+ }
+ printf("D-Cache Size: ");
+ switch (MCF5XXX_D1_DCSIZ(d1))
+ {
+ case 0:
+ printf("None\n");
+ break;
+ case 1:
+ printf("512B\n");
+ break;
+ case 2:
+ printf("1KB\n");
+ break;
+ case 3:
+ printf("2KB\n");
+ break;
+ case 4:
+ printf("4KB\n");
+ break;
+ case 5:
+ printf("8KB\n");
+ break;
+ case 6:
+ printf("16KB\n");
+ break;
+ case 7:
+ printf("32KB\n");
+ break;
+ case 8:
+ printf("64KB\n");
+ break;
+ default:
+ printf("Reserved\n");
+ }
+ printf("\n");
+#else
+ /* Remove compiler warnings. */
+ ( void ) d0;
+ ( void ) d1;
+#endif
+}
+
+/********************************************************************/
+void
+mcf5xxx_irq_enable (void)
+{
+ asm_set_ipl(0);
+}
+/********************************************************************/
+void
+mcf5xxx_irq_disable (void)
+{
+ asm_set_ipl(7);
+}
+/********************************************************************/
+/*
+ * Write new interrupt vector handler into the vector table
+ * Return previous handler address
+ */
+
+ADDRESS
+mcf5xxx_set_handler (int vector, ADDRESS new_handler)
+{
+ ADDRESS old_handler;
+ extern uint32 __VECTOR_RAM[];
+
+ old_handler = (ADDRESS) __VECTOR_RAM[vector];
+ __VECTOR_RAM[vector] = (uint32)new_handler;
+ return old_handler;
+}
+
+/********************************************************************/
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5xxx.h b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5xxx.h new file mode 100644 index 00000000..171c6fed --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5xxx.h @@ -0,0 +1,283 @@ +/*
+ * File: mcf5xxx.h
+ * Purpose: Definitions common to all ColdFire processors
+ *
+ * Notes:
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#ifndef _CPU_MCF5XXX_H
+#define _CPU_MCF5XXX_H
+
+/***********************************************************************/
+/*
+ * Misc. Defines
+ */
+#ifdef FALSE
+#undef FALSE
+#endif
+#define FALSE (0)
+
+#ifdef TRUE
+#undef TRUE
+#endif
+#define TRUE (1)
+
+#ifdef NULL
+#undef NULL
+#endif
+#define NULL (0)
+
+#ifdef ON
+#undef ON
+#endif
+#define ON (1)
+
+#ifdef OFF
+#undef OFF
+#endif
+#define OFF (0)
+
+/***********************************************************************/
+/*
+ * The basic data types
+ */
+typedef unsigned char uint8; /* 8 bits */
+typedef unsigned short int uint16; /* 16 bits */
+typedef unsigned long int uint32; /* 32 bits */
+
+typedef char int8; /* 8 bits */
+typedef short int int16; /* 16 bits */
+typedef int int32; /* 32 bits */
+
+typedef volatile int8 vint8; /* 8 bits */
+typedef volatile int16 vint16; /* 16 bits */
+typedef volatile int32 vint32; /* 32 bits */
+
+typedef volatile uint8 vuint8; /* 8 bits */
+typedef volatile uint16 vuint16; /* 16 bits */
+typedef volatile uint32 vuint32; /* 32 bits */
+
+/***********************************************************************/
+/*
+ * Common M68K & ColdFire definitions
+ */
+#define ADDRESS uint32
+#define INSTRUCTION uint16
+#define ILLEGAL 0x4AFC
+#define CPU_WORD_SIZE 16
+
+/* Status Register */
+#define MCF5XXX_SR_T (0x8000)
+#define MCF5XXX_SR_S (0x2000)
+#define MCF5XXX_SR_M (0x1000)
+#define MCF5XXX_SR_IPL (0x0700)
+#define MCF5XXX_SR_IPL_0 (0x0000)
+#define MCF5XXX_SR_IPL_1 (0x0100)
+#define MCF5XXX_SR_IPL_2 (0x0200)
+#define MCF5XXX_SR_IPL_3 (0x0300)
+#define MCF5XXX_SR_IPL_4 (0x0400)
+#define MCF5XXX_SR_IPL_5 (0x0500)
+#define MCF5XXX_SR_IPL_6 (0x0600)
+#define MCF5XXX_SR_IPL_7 (0x0700)
+#define MCF5XXX_SR_X (0x0010)
+#define MCF5XXX_SR_N (0x0008)
+#define MCF5XXX_SR_Z (0x0004)
+#define MCF5XXX_SR_V (0x0002)
+#define MCF5XXX_SR_C (0x0001)
+
+/* Cache Control Register */
+#define MCF5XXX_CACR_CENB (0x80000000)
+#define MCF5XXX_CACR_DEC (0x80000000)
+#define MCF5XXX_CACR_DW (0x40000000)
+#define MCF5XXX_CACR_DESB (0x20000000)
+#define MCF5XXX_CACR_CPDI (0x10000000)
+#define MCF5XXX_CACR_DDPI (0x10000000)
+#define MCF5XXX_CACR_CPD (0x10000000)
+#define MCF5XXX_CACR_CFRZ (0x08000000)
+#define MCF5XXX_CACR_DHLCK (0x08000000)
+#define MCF5XXX_CACR_DDCM_WT (0x00000000)
+#define MCF5XXX_CACR_DDCM_CB (0x02000000)
+#define MCF5XXX_CACR_DDCM_IP (0x04000000)
+#define MCF5XXX_CACR_DDCM_II (0x06000000)
+#define MCF5XXX_CACR_CINV (0x01000000)
+#define MCF5XXX_CACR_DCINVA (0x01000000)
+#define MCF5XXX_CACR_DIDI (0x00800000)
+#define MCF5XXX_CACR_DDSP (0x00800000)
+#define MCF5XXX_CACR_DISD (0x00400000)
+#define MCF5XXX_CACR_INVI (0x00200000)
+#define MCF5XXX_CACR_INVD (0x00100000)
+#define MCF5XXX_CACR_BEC (0x00080000)
+#define MCF5XXX_CACR_BCINVA (0x00040000)
+#define MCF5XXX_CACR_IEC (0x00008000)
+#define MCF5XXX_CACR_DNFB (0x00002000)
+#define MCF5XXX_CACR_IDPI (0x00001000)
+#define MCF5XXX_CACR_IHLCK (0x00000800)
+#define MCF5XXX_CACR_CEIB (0x00000400)
+#define MCF5XXX_CACR_IDCM (0x00000400)
+#define MCF5XXX_CACR_DCM_WR (0x00000000)
+#define MCF5XXX_CACR_DCM_CB (0x00000100)
+#define MCF5XXX_CACR_DCM_IP (0x00000200)
+#define MCF5XXX_CACR_DCM (0x00000200)
+#define MCF5XXX_CACR_DCM_II (0x00000300)
+#define MCF5XXX_CACR_DBWE (0x00000100)
+#define MCF5XXX_CACR_ICINVA (0x00000100)
+#define MCF5XXX_CACR_IDSP (0x00000080)
+#define MCF5XXX_CACR_DWP (0x00000020)
+#define MCF5XXX_CACR_EUSP (0x00000020)
+#define MCF5XXX_CACR_EUST (0x00000020)
+#define MCF5XXX_CACR_DF (0x00000010)
+#define MCF5XXX_CACR_CLNF_00 (0x00000000)
+#define MCF5XXX_CACR_CLNF_01 (0x00000002)
+#define MCF5XXX_CACR_CLNF_10 (0x00000004)
+#define MCF5XXX_CACR_CLNF_11 (0x00000006)
+
+/* Access Control Register */
+#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
+#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
+#define MCF5XXX_ACR_AM_4G (0x00FF0000)
+#define MCF5XXX_ACR_AM_2G (0x007F0000)
+#define MCF5XXX_ACR_AM_1G (0x003F0000)
+#define MCF5XXX_ACR_AM_1024M (0x003F0000)
+#define MCF5XXX_ACR_AM_512M (0x001F0000)
+#define MCF5XXX_ACR_AM_256M (0x000F0000)
+#define MCF5XXX_ACR_AM_128M (0x00070000)
+#define MCF5XXX_ACR_AM_64M (0x00030000)
+#define MCF5XXX_ACR_AM_32M (0x00010000)
+#define MCF5XXX_ACR_AM_16M (0x00000000)
+#define MCF5XXX_ACR_EN (0x00008000)
+#define MCF5XXX_ACR_SM_USER (0x00000000)
+#define MCF5XXX_ACR_SM_SUPER (0x00002000)
+#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
+#define MCF5XXX_ACR_ENIB (0x00000080)
+#define MCF5XXX_ACR_CM (0x00000040)
+#define MCF5XXX_ACR_DCM_WR (0x00000000)
+#define MCF5XXX_ACR_DCM_CB (0x00000020)
+#define MCF5XXX_ACR_DCM_IP (0x00000040)
+#define MCF5XXX_ACR_DCM_II (0x00000060)
+#define MCF5XXX_ACR_CM (0x00000040)
+#define MCF5XXX_ACR_BWE (0x00000020)
+#define MCF5XXX_ACR_WP (0x00000004)
+
+/* RAM Base Address Register */
+#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
+#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
+#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
+#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
+#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
+#define MCF5XXX_RAMBAR_WP (0x00000100)
+#define MCF5XXX_RAMBAR_CI (0x00000020)
+#define MCF5XXX_RAMBAR_SC (0x00000010)
+#define MCF5XXX_RAMBAR_SD (0x00000008)
+#define MCF5XXX_RAMBAR_UC (0x00000004)
+#define MCF5XXX_RAMBAR_UD (0x00000002)
+#define MCF5XXX_RAMBAR_V (0x00000001)
+
+/* Read macros for D0/D1 reset values */
+#define MCF5XXX_D0_PF(x) (((x)&0xFF000000)>>24)
+#define MCF5XXX_D0_VER(x) (((x)&0x00F00000)>>20)
+#define MCF5XXX_D0_REV(x) (((x)&0x000F0000)>>16)
+#define MCF5XXX_D0_MAC(x) ((x)&0x00008000)
+#define MCF5XXX_D0_DIV(x) ((x)&0x00004000)
+#define MCF5XXX_D0_EMAC(x) ((x)&0x00002000)
+#define MCF5XXX_D0_FPU(x) ((x)&0x00001000)
+#define MCF5XXX_D0_MMU(x) ((x)&0x00000800)
+#define MCF5XXX_D0_ISA(x) (((x)&0x000000F0)>>4)
+#define MCF5XXX_D0_DEBUG(x) (((x)&0x0000000F)>>0)
+#define MCF5XXX_D1_CL(x) (((x)&0xC0000000)>>30)
+#define MCF5XXX_D1_ICA(x) (((x)&0x30000000)>>28)
+#define MCF5XXX_D1_ICSIZ(x) (((x)&0x0F000000)>>24)
+#define MCF5XXX_D1_RAM0SIZ(x) (((x)&0x00F00000)>>20)
+#define MCF5XXX_D1_ROM0SIZ(x) (((x)&0x000F0000)>>16)
+#define MCF5XXX_D1_BUSW(x) (((x)&0x0000C000)>>14)
+#define MCF5XXX_D1_DCA(x) (((x)&0x00003000)>>12)
+#define MCF5XXX_D1_DCSIZ(x) (((x)&0x00000F00)>>8)
+#define MCF5XXX_D1_RAM1SIZ(x) (((x)&0x000000F0)>>4)
+#define MCF5XXX_D1_ROM1SIZ(x) (((x)&0x0000000F)>>0)
+
+/***********************************************************************/
+/*
+ * The ColdFire family of processors has a simplified exception stack
+ * frame that looks like the following:
+ *
+ * 3322222222221111 111111
+ * 1098765432109876 5432109876543210
+ * 8 +----------------+----------------+
+ * | Program Counter |
+ * 4 +----------------+----------------+
+ * |FS/Fmt/Vector/FS| SR |
+ * SP --> 0 +----------------+----------------+
+ *
+ * The stack self-aligns to a 4-byte boundary at an exception, with
+ * the FS/Fmt/Vector/FS field indicating the size of the adjustment
+ * (SP += 0,1,2,3 bytes).
+ */
+#define MCF5XXX_RD_SF_FORMAT(PTR) \
+ ((*((uint16 *)(PTR)) >> 12) & 0x00FF)
+
+#define MCF5XXX_RD_SF_VECTOR(PTR) \
+ ((*((uint16 *)(PTR)) >> 2) & 0x00FF)
+
+#define MCF5XXX_RD_SF_FS(PTR) \
+ ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
+
+#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
+#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
+
+/********************************************************************/
+/*
+ * Functions provided in mcf5xxx.s
+ */
+int asm_set_ipl (uint32);
+void mcf5xxx_exe_wdebug (void *);
+void mcf5xxx_wr_sr (uint32);
+void mcf5xxx_wr_cacr (uint32);
+void mcf5xxx_wr_asid (uint32);
+void mcf5xxx_wr_acr0 (uint32);
+void mcf5xxx_wr_acr1 (uint32);
+void mcf5xxx_wr_acr2 (uint32);
+void mcf5xxx_wr_acr3 (uint32);
+void mcf5xxx_wr_mmubar (uint32);
+void mcf5xxx_wr_other_a7 (uint32);
+void mcf5xxx_wr_other_sp (uint32);
+void mcf5xxx_wr_vbr (uint32);
+void mcf5xxx_wr_macsr (uint32);
+void mcf5xxx_wr_mask (uint32);
+void mcf5xxx_wr_acc0 (uint32);
+void mcf5xxx_wr_accext01 (uint32);
+void mcf5xxx_wr_accext23 (uint32);
+void mcf5xxx_wr_acc1 (uint32);
+void mcf5xxx_wr_acc2 (uint32);
+void mcf5xxx_wr_acc3 (uint32);
+void mcf5xxx_wr_pc (uint32);
+void mcf5xxx_wr_rombar0 (uint32);
+void mcf5xxx_wr_rombar1 (uint32);
+void mcf5xxx_wr_rambar0 (uint32);
+void mcf5xxx_wr_rambar1 (uint32);
+void mcf5xxx_wr_mpcr (uint32);
+void mcf5xxx_wr_secmbar (uint32);
+void mcf5xxx_wr_mbar1 (uint32);
+void mcf5xxx_wr_mbar (uint32);
+void mcf5xxx_wr_mbar0 (uint32);
+void mcf5xxx_move_line (ADDRESS, ADDRESS);
+
+/*
+ * Functions provided in mcf5xxx.c
+ */
+void mcf5xxx_exception_handler (void *);
+void mcf5xxx_interpret_d0d1 (int, int);
+void mcf5xxx_irq_enable (void);
+void mcf5xxx_irq_disable (void);
+ADDRESS mcf5xxx_set_handler (int, ADDRESS);
+
+/*
+ * Functions provided by processor specific C file
+ */
+void cpu_handle_interrupt (int);
+
+/********************************************************************/
+
+#endif /* _CPU_MCF5XXX_H */
+
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5xxx_lo.s b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5xxx_lo.s new file mode 100644 index 00000000..0e843828 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5xxx_lo.s @@ -0,0 +1,342 @@ +/*
+ * File: mcf5xxx.s
+ * Purpose: Lowest level routines for all ColdFire processors.
+ *
+ * Notes:
+ *
+ * License: All software covered by license agreement in -
+ * docs/Freescale_Software_License.pdf
+ */
+
+#define mcf5xxx_exception_handler _mcf5xxx_exception_handler
+
+ .extern mcf5xxx_exception_handler
+
+ .global asm_exception_handler
+ .global _asm_exception_handler
+ .global asm_set_ipl
+ .global _asm_set_ipl
+ .global mcf5xxx_exe_wdebug
+ .global _mcf5xxx_exe_wdebug
+ .global mcf5xxx_move_line //added by Mac
+ .global _mcf5xxx_move_line //added by Mac
+ .global mcf5xxx_wr_cacr
+ .global _mcf5xxx_wr_cacr
+ .global mcf5xxx_wr_asid
+ .global _mcf5xxx_wr_asid
+ .global mcf5xxx_wr_acr0
+ .global _mcf5xxx_wr_acr0
+ .global mcf5xxx_wr_acr1
+ .global _mcf5xxx_wr_acr1
+ .global mcf5xxx_wr_acr2
+ .global _mcf5xxx_wr_acr2
+ .global mcf5xxx_wr_acr3
+ .global _mcf5xxx_wr_acr3
+ .global mcf5xxx_wr_mmubar
+ .global _mcf5xxx_wr_mmubar
+ .global mcf5xxx_wr_other_a7
+ .global _mcf5xxx_wr_other_a7
+ .global mcf5xxx_wr_vbr
+ .global _mcf5xxx_wr_vbr
+ .global mcf5xxx_wr_macsr
+ .global _mcf5xxx_wr_macsr
+ .global mcf5xxx_wr_mask
+ .global _mcf5xxx_wr_mask
+ .global mcf5xxx_wr_acc0
+ .global _mcf5xxx_wr_acc0
+ .global mcf5xxx_wr_accext01
+ .global _mcf5xxx_wr_accext01
+ .global mcf5xxx_wr_accext23
+ .global _mcf5xxx_wr_accext23
+ .global mcf5xxx_wr_acc1
+ .global _mcf5xxx_wr_acc1
+ .global mcf5xxx_wr_acc2
+ .global _mcf5xxx_wr_acc2
+ .global mcf5xxx_wr_acc3
+ .global _mcf5xxx_wr_acc3
+ .global mcf5xxx_wr_sr
+ .global _mcf5xxx_wr_sr
+ .global mcf5xxx_wr_pc
+ .global _mcf5xxx_wr_pc
+ .global mcf5xxx_wr_rombar0
+ .global _mcf5xxx_wr_rombar0
+ .global mcf5xxx_wr_rombar1
+ .global _mcf5xxx_wr_rombar1
+ .global mcf5xxx_wr_rambar0
+ .global _mcf5xxx_wr_rambar0
+ .global mcf5xxx_wr_rambar1
+ .global _mcf5xxx_wr_rambar1
+ .global mcf5xxx_wr_mpcr
+ .global _mcf5xxx_wr_mpcr
+ .global mcf5xxx_wr_secmbar
+ .global _mcf5xxx_wr_secmbar
+ .global mcf5xxx_wr_mbar
+ .global _mcf5xxx_wr_mbar
+
+ .text
+
+/********************************************************************
+ * This routine is the lowest-level exception handler.
+ */
+
+asm_exception_handler:
+_asm_exception_handler:
+ lea -16(SP),SP
+ movem.l D0-D1/A0-A1,(SP)
+ lea 16(SP),A1
+ move.l A1,-(SP)
+ jsr mcf5xxx_exception_handler
+ lea 4(SP),SP
+ movem.l (SP),D0-D1/A0-A1
+ lea 16(SP),SP
+ rte
+
+/********************************************************************/
+/*
+ * This routines changes the IPL to the value passed into the routine.
+ * It also returns the old IPL value back.
+ * Calling convention from C:
+ * old_ipl = asm_set_ipl(new_ipl);
+ * For the Diab Data C compiler, it passes return value thru D0.
+ * Note that only the least significant three bits of the passed
+ * value are used.
+ */
+
+asm_set_ipl:
+_asm_set_ipl:
+ link A6,#-8
+ movem.l D6-D7,(SP)
+
+ move.w SR,D7 /* current sr */
+
+ move.l D7,D0 /* prepare return value */
+ andi.l #0x0700,D0 /* mask out IPL */
+ lsr.l #8,D0 /* IPL */
+
+ move.l 8(A6),D6 /* get argument */
+ andi.l #0x07,D6 /* least significant three bits */
+ lsl.l #8,D6 /* move over to make mask */
+
+ andi.l #0x0000F8FF,D7 /* zero out current IPL */
+ or.l D6,D7 /* place new IPL in sr */
+ move.w D7,SR
+
+ movem.l (SP),D6-D7
+ lea 8(SP),SP
+ unlk A6
+ rts
+
+/********************************************************************/
+/*
+ * These routines execute special ColdFire instructions
+ */
+
+mcf5xxx_exe_wdebug:
+_mcf5xxx_exe_wdebug:
+ move.l 4(sp),a0
+ wdebug.l (a0)
+ rts
+
+ mcf5xxx_move_line:
+_mcf5xxx_move_line:
+ lea.l -24(sp),sp
+ movem.l d0-d3/a0-a1,(sp)
+ movea.l 28(sp),a0 /* source in a0 */
+ movea.l 32(sp),a1 /* destination in a1 */
+ movem.l (a0),d0-d3 /* move line from source */
+ movem.l d0-d3,(a1) /* move line to destination */
+ movem.l (sp),d0-d3/a0-a1
+ lea.l 24(sp),sp
+ rts
+
+
+/********************************************************************/
+/*
+ * These routines write to the special purpose registers in the ColdFire
+ * core. Since these registers are write-only in the supervisor model,
+ * no corresponding read routines exist.
+ */
+
+mcf5xxx_wr_sr:
+_mcf5xxx_wr_sr:
+ move.l 4(SP),D0
+ move.w D0,SR
+ rts
+
+mcf5xxx_wr_cacr:
+_mcf5xxx_wr_cacr:
+ move.l 4(SP),D0
+ .long 0x4e7b0002 /* movec d0,cacr */
+ nop
+ rts
+
+mcf5xxx_wr_asid:
+_mcf5xxx_wr_asid:
+ move.l 4(SP),D0
+ .long 0x4e7b0003 /* movec d0,asid */
+ nop
+ rts
+
+mcf5xxx_wr_acr0:
+_mcf5xxx_wr_acr0:
+ move.l 4(SP),D0
+ .long 0x4e7b0004 /* movec d0,ACR0 */
+ nop
+ rts
+
+mcf5xxx_wr_acr1:
+_mcf5xxx_wr_acr1:
+ move.l 4(SP),D0
+ .long 0x4e7b0005 /* movec d0,ACR1 */
+ nop
+ rts
+
+mcf5xxx_wr_acr2:
+_mcf5xxx_wr_acr2:
+ move.l 4(SP),D0
+ .long 0x4e7b0006 /* movec d0,ACR2 */
+ nop
+ rts
+
+mcf5xxx_wr_acr3:
+_mcf5xxx_wr_acr3:
+ move.l 4(SP),D0
+ .long 0x4e7b0007 /* movec d0,ACR3 */
+ nop
+ rts
+
+mcf5xxx_wr_mmubar:
+_mcf5xxx_wr_mmubar:
+ move.l 4(SP),D0
+ .long 0x4e7b0008 /* movec d0,MBAR */
+ nop
+ rts
+
+mcf5xxx_wr_other_a7:
+_mcf5xxx_wr_other_a7:
+ move.l 4(SP),D0
+ .long 0x4e7b0800 /* movec d0,OTHER_A7 */
+ nop
+ rts
+
+mcf5xxx_wr_vbr:
+_mcf5xxx_wr_vbr:
+ move.l 4(SP),D0
+ .long 0x4e7b0801 /* movec d0,VBR */
+ nop
+ rts
+
+mcf5xxx_wr_macsr:
+_mcf5xxx_wr_macsr:
+ move.l 4(SP),D0
+ .long 0x4e7b0804 /* movec d0,MACSR */
+ nop
+ rts
+
+mcf5xxx_wr_mask:
+_mcf5xxx_wr_mask:
+ move.l 4(SP),D0
+ .long 0x4e7b0805 /* movec d0,MASK */
+ nop
+ rts
+
+mcf5xxx_wr_acc0:
+_mcf5xxx_wr_acc0:
+ move.l 4(SP),D0
+ .long 0x4e7b0806 /* movec d0,ACC0 */
+ nop
+ rts
+
+mcf5xxx_wr_accext01:
+_mcf5xxx_wr_accext01:
+ move.l 4(SP),D0
+ .long 0x4e7b0807 /* movec d0,ACCEXT01 */
+ nop
+ rts
+
+mcf5xxx_wr_accext23:
+_mcf5xxx_wr_accext23:
+ move.l 4(SP),D0
+ .long 0x4e7b0808 /* movec d0,ACCEXT23 */
+ nop
+ rts
+
+mcf5xxx_wr_acc1:
+_mcf5xxx_wr_acc1:
+ move.l 4(SP),D0
+ .long 0x4e7b0809 /* movec d0,ACC1 */
+ nop
+ rts
+
+mcf5xxx_wr_acc2:
+_mcf5xxx_wr_acc2:
+ move.l 4(SP),D0
+ .long 0x4e7b080A /* movec d0,ACC2 */
+ nop
+ rts
+
+mcf5xxx_wr_acc3:
+_mcf5xxx_wr_acc3:
+ move.l 4(SP),D0
+ .long 0x4e7b080B /* movec d0,ACC3 */
+ nop
+ rts
+
+mcf5xxx_wr_pc:
+_mcf5xxx_wr_pc:
+ move.l 4(SP),D0
+ .long 0x4e7b080F /* movec d0,PC */
+ nop
+ rts
+
+mcf5xxx_wr_rombar0:
+_mcf5xxx_wr_rombar0:
+ move.l 4(SP),D0
+ .long 0x4e7b0C00 /* movec d0,ROMBAR0 */
+ nop
+ rts
+
+mcf5xxx_wr_rombar1:
+_mcf5xxx_wr_rombar1:
+ move.l 4(SP),D0
+ .long 0x4e7b0C01 /* movec d0,ROMBAR1 */
+ nop
+ rts
+
+mcf5xxx_wr_rambar0:
+_mcf5xxx_wr_rambar0:
+ move.l 4(SP),D0
+ .long 0x4e7b0C04 /* movec d0,RAMBAR0 */
+ nop
+ rts
+
+mcf5xxx_wr_rambar1:
+_mcf5xxx_wr_rambar1:
+ move.l 4(SP),D0
+ .long 0x4e7b0C05 /* movec d0,RAMBAR1 */
+ nop
+ rts
+
+mcf5xxx_wr_mpcr:
+_mcf5xxx_wr_mpcr:
+ move.l 4(SP),D0
+ .long 0x4e7b0C0C /* movec d0,MPCR */
+ nop
+ rts
+
+mcf5xxx_wr_secmbar:
+_mcf5xxx_wr_secmbar:
+ move.l 4(SP),D0
+ .long 0x4e7b0C0E /* movec d0,MBAR1 */
+ nop
+ rts
+
+mcf5xxx_wr_mbar:
+_mcf5xxx_wr_mbar:
+ move.l 4(SP),D0
+ .long 0x4e7b0C0F /* movec d0,MBAR0 */
+ nop
+ rts
+
+/********************************************************************/
+ .end
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/lcf/MCF52259_INTERNAL_FLASH.lcf b/Demo/ColdFire_MCF52259_CodeWarrior/lcf/MCF52259_INTERNAL_FLASH.lcf new file mode 100644 index 00000000..eaaca876 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/lcf/MCF52259_INTERNAL_FLASH.lcf @@ -0,0 +1,103 @@ +# NOTE: The debugger uses the Illegal Instruction Vector to stop.
+# A small subroutine is written at the location VBR+0x408-VBR+0x40B
+# to handle the exception. The Illegal Instruction Vector in
+# the the vector table at VBR+0x10 is then pointed to it. When the
+# debugger encounters an illegal instruction, it jumps to this
+# subroutine, which ends with an RTE, then exits.
+# Do not overwrite this area of memory otherwise the debugger may not
+# exit properly.
+# */
+
+MEMORY
+{
+ vectorflash(RX) : ORIGIN = 0x00000000, LENGTH = 0x00000418
+
+ flash (RX) : ORIGIN = 0x00000420, LENGTH = 0x0007FC00
+ vectorram(RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000400
+ sram (RWX) : ORIGIN = 0x20000400, LENGTH = 0x0000FA00
+ ipsbar (RWX) : ORIGIN = 0x40000000, LENGTH = 0x0
+}
+
+SECTIONS
+{
+ .ipsbar : {} > ipsbar
+
+ .vectorflash :
+ {
+ mcf5225x_vectors.s (.text)
+ } > vectorflash
+
+ .flash :
+ {
+ *(.text)
+ . = ALIGN(0x10);
+ *(.rodata)
+
+ ___DATA_ROM = .;
+ } > flash
+
+ .data : AT(___DATA_ROM)
+ {
+ ___DATA_RAM = . ;
+
+ *(.exception)
+ . = ALIGN(0x10);
+ __exception_table_start__ = .;
+ EXCEPTION
+ __exception_table_end__ = .;
+
+ ___sinit__ = .;
+ STATICINIT
+
+ *(.data)
+ *(.relocate_code)
+ . = ALIGN (0x10);
+ ___DATA_END = .;
+
+ __START_SDATA = .;
+ *(.sdata)
+
+ . = ALIGN (0x10);
+ __END_SDATA = .;
+
+ __SDA_BASE = .;
+ . = ALIGN(0x10);
+ } > sram
+
+ .bss :
+ {
+ . = ALIGN(0x10);
+ __START_SBSS = .;
+ *(.sbss)
+ *(SCOMMON)
+ __END_SBSS = .;
+
+ . = ALIGN(0x10);
+ __START_BSS = .;
+ *(.bss)
+ *(COMMON)
+ __END_BSS = .;
+ ___BSS_START = __START_SBSS;
+ ___BSS_END = __END_BSS;
+ . = ALIGN(0x10);
+
+ } >> sram
+
+ ___FLASH = ADDR(.vectorflash);
+ ___FLASH_SIZE = 0x00080000;
+ ___SRAM = 0x20000400;
+ ___SRAM_SIZE = 0x0000FC00;
+
+ ___VECTOR_RAM = 0x20000000;
+ ___IPSBAR = ADDR(.ipsbar);
+
+ ___SP_SIZE = 0x200;
+ ___HEAP_START = .;
+ ___HEAP_END = ___SRAM + ___SRAM_SIZE - ___SP_SIZE;
+ ___SP_END = ___HEAP_END;
+ ___SP_INIT = ___SP_END + ___SP_SIZE;
+
+ ___heap_addr = ___HEAP_START;
+ ___heap_size = ___HEAP_END - ___HEAP_START ;
+ __SP_INIT = ___SP_INIT;
+}
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/lwipopts.h b/Demo/ColdFire_MCF52259_CodeWarrior/lwipopts.h new file mode 100644 index 00000000..3849907d --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/lwipopts.h @@ -0,0 +1,238 @@ +/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+#define TCPIP_THREAD_NAME "tcp/ip"
+#define TCPIP_THREAD_STACKSIZE 350
+#define TCPIP_THREAD_PRIO 2
+
+#define DEFAULT_THREAD_STACKSIZE 200
+#define DEFAULT_THREAD_PRIO 1
+
+#define ETH_PAD_SIZE 2
+
+#define NOT_LWIP_DEBUG 0
+#define DBG_TYPES_ON 0x00
+#define LWIP_DBG_TYPES_ON LWIP_DBG_OFF
+
+#define ETHARP_DEBUG LWIP_DBG_OFF
+#define NETIF_DEBUG LWIP_DBG_OFF
+#define PBUF_DEBUG LWIP_DBG_OFF
+#define API_LIB_DEBUG LWIP_DBG_OFF
+#define API_MSG_DEBUG LWIP_DBG_OFF
+#define SOCKETS_DEBUG LWIP_DBG_OFF
+#define ICMP_DEBUG LWIP_DBG_OFF
+#define IGMP_DEBUG LWIP_DBG_OFF
+#define INET_DEBUG LWIP_DBG_OFF
+#define IP_DEBUG LWIP_DBG_OFF
+#define IP_REASS_DEBUG LWIP_DBG_OFF
+#define RAW_DEBUG LWIP_DBG_OFF
+#define MEM_DEBUG LWIP_DBG_OFF
+#define MEMP_DEBUG LWIP_DBG_OFF
+#define SYS_DEBUG LWIP_DBG_OFF
+#define TCP_DEBUG LWIP_DBG_OFF
+#define TCP_INPUT_DEBUG LWIP_DBG_OFF
+#define TCP_FR_DEBUG LWIP_DBG_OFF
+#define TCP_RTO_DEBUG LWIP_DBG_OFF
+#define TCP_CWND_DEBUG LWIP_DBG_OFF
+#define TCP_WND_DEBUG LWIP_DBG_OFF
+#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
+#define TCP_RST_DEBUG LWIP_DBG_OFF
+#define TCP_QLEN_DEBUG LWIP_DBG_OFF
+#define UDP_DEBUG LWIP_DBG_OFF
+#define TCPIP_DEBUG LWIP_DBG_OFF
+#define PPP_DEBUG LWIP_DBG_OFF
+#define SLIP_DEBUG LWIP_DBG_OFF
+#define DHCP_DEBUG LWIP_DBG_OFF
+#define AUTOIP_DEBUG LWIP_DBG_OFF
+#define SNMP_MSG_DEBUG LWIP_DBG_OFF
+#define SNMP_MIB_DEBUG LWIP_DBG_OFF
+#define DNS_DEBUG LWIP_DBG_OFF
+#define LWIP_NOASSERT 0
+
+#define ETHARP_TRUST_IP_MAC 0
+#define LWIP_UDP 0
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#define SYS_LIGHTWEIGHT_PROT 1
+
+/*
+ ------------------------------------
+ ---------- Memory options ----------
+ ------------------------------------
+*/
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ * 4 byte alignment -> #define MEM_ALIGNMENT 4
+ * 2 byte alignment -> #define MEM_ALIGNMENT 2
+ */
+#define MEM_ALIGNMENT 4
+
+/**
+ * MEM_SIZE: the size of the heap memory. If the application will send
+ * a lot of data that needs to be copied, this should be set high.
+ */
+#define MEM_SIZE (8*1024)
+
+/*
+ ------------------------------------------------
+ ---------- Internal Memory Pool Sizes ----------
+ ------------------------------------------------
+*/
+/**
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
+ * If the application sends a lot of data out of ROM (or other static memory),
+ * this should be set high.
+ */
+#define MEMP_NUM_PBUF 20
+
+/**
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#define MEMP_NUM_TCP_PCB 10
+
+/**
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
+ * (requires the LWIP_TCP option)
+ */
+#define MEMP_NUM_TCP_SEG 8
+
+/**
+ * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
+ * (requires NO_SYS==0)
+ */
+#define MEMP_NUM_SYS_TIMEOUT 5
+
+/**
+ * MEMP_NUM_NETBUF: the number of struct netbufs.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#define MEMP_NUM_NETBUF 4
+
+/**
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
+ */
+#define PBUF_POOL_SIZE 4
+
+
+/*
+ ----------------------------------
+ ---------- Pbuf options ----------
+ ----------------------------------
+*/
+
+/**
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
+ * designed to accomodate single full size TCP frame in one pbuf, including
+ * TCP_MSS, IP header, and link header.
+ */
+#define PBUF_POOL_BUFSIZE 1500
+
+/*
+ ---------------------------------
+ ---------- TCP options ----------
+ ---------------------------------
+*/
+/**
+ * LWIP_TCP==1: Turn on TCP.
+ */
+#define LWIP_TCP 1
+
+/* TCP Maximum segment size. */
+#define TCP_MSS 1500
+
+/* TCP sender buffer space (bytes). */
+#define TCP_SND_BUF 1500
+
+/**
+ * TCP_WND: The size of a TCP window.
+ */
+#define TCP_WND 1500
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#define TCP_SYNMAXRTX 4
+
+/*
+ ---------------------------------
+ ---------- RAW options ----------
+ ---------------------------------
+*/
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#define LWIP_RAW 0
+
+
+/*
+ ------------------------------------
+ ---------- Socket options ----------
+ ------------------------------------
+*/
+/**
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
+ */
+#define LWIP_SOCKET 0
+
+
+/*
+ ----------------------------------------
+ ---------- Statistics options ----------
+ ----------------------------------------
+*/
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#define LWIP_STATS 0
+
+/*
+ ----------------------------------
+ ---------- DHCP options ----------
+ ----------------------------------
+*/
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#define LWIP_DHCP 0
+
+
+#define LWIP_PROVIDE_ERRNO 0
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/main.c b/Demo/ColdFire_MCF52259_CodeWarrior/main.c new file mode 100644 index 00000000..1d15f134 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/main.c @@ -0,0 +1,453 @@ +/*
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.
+
+ This file is part of the FreeRTOS.org distribution.
+
+ FreeRTOS.org is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ FreeRTOS.org is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with FreeRTOS.org; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ A special exception to the GPL can be applied should you wish to distribute
+ a combined work that includes FreeRTOS.org, without being obliged to provide
+ the source code for any proprietary components. See the licensing section
+ of http://www.FreeRTOS.org for full details of how and when the exception
+ can be applied.
+
+ ***************************************************************************
+ ***************************************************************************
+ * *
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
+ * and even write all or part of your application on your behalf. *
+ * See http://www.OpenRTOS.com for details of the services we provide to *
+ * expedite your project. *
+ * *
+ ***************************************************************************
+ ***************************************************************************
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler. The WEB
+ * documentation provides more details of the standard demo application tasks.
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Web server" - Very basic demonstration of the lwIP stack. The WEB server
+ * simply generates a page that shows the current state of all the tasks within
+ * the system, including the high water mark of each task stack. The high water
+ * mark is displayed as the amount of stack that has never been used, so the
+ * closer the value is to zero the closer the task has come to overflowing its
+ * stack. The IP address and net mask are set within FreeRTOSConfig.h.
+ *
+ * "Check" task - This only executes every five seconds but has a high priority
+ * to ensure it gets processor time. Its main function is to check that all the
+ * standard demo tasks are still operational. While no errors have been
+ * discovered the check task will toggle an LED every 5 seconds - the toggle
+ * rate increasing to 500ms being a visual indication that at least one task has
+ * reported unexpected behaviour.
+ *
+ * "Reg test" tasks - These fill the registers with known values, then check
+ * that each register still contains its expected value. Each task uses
+ * different values. The tasks run with very low priority so get preempted very
+ * frequently. A register containing an unexpected value is indicative of an
+ * error in the context switching mechanism.
+ *
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* Demo app includes. */
+#include "BlockQ.h"
+#include "death.h"
+#include "flash.h"
+#include "partest.h"
+#include "semtest.h"
+#include "PollQ.h"
+#include "GenQTest.h"
+#include "QPeek.h"
+#include "recmutex.h"
+
+/*-----------------------------------------------------------*/
+
+/* The time between cycles of the 'check' functionality - as described at the
+top of this file. */
+#define mainNO_ERROR_PERIOD ( ( portTickType ) 5000 / portTICK_RATE_MS )
+
+/* The rate at which the LED controlled by the 'check' task will flash should an
+error have been detected. */
+#define mainERROR_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
+
+/* The LED controlled by the 'check' task. */
+#define mainCHECK_LED ( 3 )
+
+/* ComTest constants - there is no free LED for the comtest tasks. */
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 )
+#define mainCOM_TEST_LED ( 5 )
+
+/* Task priorities. */
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainWEB_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+
+/*
+ * Configure the hardware for the demo.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * Implements the 'check' task functionality as described at the top of this
+ * file.
+ */
+static void prvCheckTask( void *pvParameters );
+
+/*
+ * Implement the 'Reg test' functionality as described at the top of this file.
+ */
+static void vRegTest1Task( void *pvParameters );
+static void vRegTest2Task( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* Counters used to detect errors within the reg test tasks. */
+static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+extern void vBasicWEBServer( void *pv );
+
+ /* Setup the hardware ready for this demo. */
+ prvSetupHardware();
+ ( void )sys_thread_new("HTTPD", vBasicWEBServer, NULL, 320, mainWEB_TASK_PRIORITY );
+
+ /* Start the standard demo tasks. */
+ vStartLEDFlashTasks( tskIDLE_PRIORITY );
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
+ vStartQueuePeekTasks();
+ vStartRecursiveMutexTasks();
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+
+ /* Start the reg test tasks - defined in this file. */
+ xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );
+
+ /* Create the check task. */
+ xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+ /* The suicide tasks must be created last as they need to know how many
+ tasks were running prior to their creation in order to ascertain whether
+ or not the correct/expected number of tasks are running at any given time. */
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+ /* Start the scheduler. */
+ vTaskStartScheduler();
+
+ /* Will only get here if there was insufficient memory to create the idle
+ task. */
+ for( ;; )
+ {
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void *pvParameters )
+{
+unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;
+portTickType xLastExecutionTime;
+
+ ( void ) pvParameters;
+
+ /* Initialise the variable used to control our iteration rate prior to
+ its first use. */
+ xLastExecutionTime = xTaskGetTickCount();
+
+ for( ;; )
+ {
+ /* Wait until it is time to run the tests again. */
+ vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );
+
+ /* Has an error been found in any task? */
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ ulError |= 0x01UL;
+ }
+
+ if( xAreQueuePeekTasksStillRunning() != pdTRUE )
+ {
+ ulError |= 0x02UL;
+ }
+
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )
+ {
+ ulError |= 0x04UL;
+ }
+
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ ulError |= 0x20UL;
+ }
+
+ if( xArePollingQueuesStillRunning() != pdTRUE )
+ {
+ ulError |= 0x40UL;
+ }
+
+ if( xIsCreateTaskStillRunning() != pdTRUE )
+ {
+ ulError |= 0x80UL;
+ }
+
+ if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ ulError |= 0x200UL;
+ }
+
+ if( ulLastRegTest1Count == ulRegTest1Counter )
+ {
+ ulError |= 0x1000UL;
+ }
+
+ if( ulLastRegTest2Count == ulRegTest2Counter )
+ {
+ ulError |= 0x1000UL;
+ }
+
+ ulLastRegTest1Count = ulRegTest1Counter;
+ ulLastRegTest2Count = ulRegTest2Counter;
+
+ /* If an error has been found then increase our cycle rate, and in so
+ going increase the rate at which the check task LED toggles. */
+ if( ulError != 0 )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ }
+
+ /* Toggle the LED each itteration. */
+ vParTestToggleLED( mainCHECK_LED );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void prvSetupHardware( void )
+{
+ portDISABLE_INTERRUPTS();
+
+ /* Setup the port used to toggle LEDs. */
+ vParTestInitialise();
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )
+{
+ /* This will get called if a stack overflow is detected during the context
+ switch. Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack
+ problems within nested interrupts, but only do this for debug purposes as
+ it will increase the context switch time. */
+
+ ( void ) pxTask;
+ ( void ) pcTaskName;
+
+ for( ;; )
+ {
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void vRegTest1Task( void *pvParameters )
+{
+ /* Sanity check - did we receive the parameter expected? */
+ if( pvParameters != &ulRegTest1Counter )
+ {
+ /* Change here so the check task can detect that an error occurred. */
+ for( ;; )
+ {
+ }
+ }
+
+ /* Set all the registers to known values, then check that each retains its
+ expected value - as described at the top of this file. If an error is
+ found then the loop counter will no longer be incremented allowing the check
+ task to recognise the error. */
+ asm volatile ( "reg_test_1_start: \n\t"
+ " moveq #1, d0 \n\t"
+ " moveq #2, d1 \n\t"
+ " moveq #3, d2 \n\t"
+ " moveq #4, d3 \n\t"
+ " moveq #5, d4 \n\t"
+ " moveq #6, d5 \n\t"
+ " moveq #7, d6 \n\t"
+ " moveq #8, d7 \n\t"
+ " move #9, a0 \n\t"
+ " move #10, a1 \n\t"
+ " move #11, a2 \n\t"
+ " move #12, a3 \n\t"
+ " move #13, a4 \n\t"
+ " move #14, a5 \n\t"
+ " move #15, a6 \n\t"
+ " \n\t"
+ " cmpi.l #1, d0 \n\t"
+ " bne reg_test_1_error \n\t"
+ " cmpi.l #2, d1 \n\t"
+ " bne reg_test_1_error \n\t"
+ " cmpi.l #3, d2 \n\t"
+ " bne reg_test_1_error \n\t"
+ " cmpi.l #4, d3 \n\t"
+ " bne reg_test_1_error \n\t"
+ " cmpi.l #5, d4 \n\t"
+ " bne reg_test_1_error \n\t"
+ " cmpi.l #6, d5 \n\t"
+ " bne reg_test_1_error \n\t"
+ " cmpi.l #7, d6 \n\t"
+ " bne reg_test_1_error \n\t"
+ " cmpi.l #8, d7 \n\t"
+ " bne reg_test_1_error \n\t"
+ " move a0, d0 \n\t"
+ " cmpi.l #9, d0 \n\t"
+ " bne reg_test_1_error \n\t"
+ " move a1, d0 \n\t"
+ " cmpi.l #10, d0 \n\t"
+ " bne reg_test_1_error \n\t"
+ " move a2, d0 \n\t"
+ " cmpi.l #11, d0 \n\t"
+ " bne reg_test_1_error \n\t"
+ " move a3, d0 \n\t"
+ " cmpi.l #12, d0 \n\t"
+ " bne reg_test_1_error \n\t"
+ " move a4, d0 \n\t"
+ " cmpi.l #13, d0 \n\t"
+ " bne reg_test_1_error \n\t"
+ " move a5, d0 \n\t"
+ " cmpi.l #14, d0 \n\t"
+ " bne reg_test_1_error \n\t"
+ " move a6, d0 \n\t"
+ " cmpi.l #15, d0 \n\t"
+ " bne reg_test_1_error \n\t"
+ " move ulRegTest1Counter, d0 \n\t"
+ " addq #1, d0 \n\t"
+ " move d0, ulRegTest1Counter \n\t"
+ " bra reg_test_1_start \n\t"
+ "reg_test_1_error: \n\t"
+ " bra reg_test_1_error \n\t"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void vRegTest2Task( void *pvParameters )
+{
+ /* Sanity check - did we receive the parameter expected? */
+ if( pvParameters != &ulRegTest2Counter )
+ {
+ /* Change here so the check task can detect that an error occurred. */
+ for( ;; )
+ {
+ }
+ }
+
+ /* Set all the registers to known values, then check that each retains its
+ expected value - as described at the top of this file. If an error is
+ found then the loop counter will no longer be incremented allowing the check
+ task to recognise the error. */
+ asm volatile ( "reg_test_2_start: \n\t"
+ " moveq #10, d0 \n\t"
+ " moveq #20, d1 \n\t"
+ " moveq #30, d2 \n\t"
+ " moveq #40, d3 \n\t"
+ " moveq #50, d4 \n\t"
+ " moveq #60, d5 \n\t"
+ " moveq #70, d6 \n\t"
+ " moveq #80, d7 \n\t"
+ " move #90, a0 \n\t"
+ " move #100, a1 \n\t"
+ " move #110, a2 \n\t"
+ " move #120, a3 \n\t"
+ " move #130, a4 \n\t"
+ " move #140, a5 \n\t"
+ " move #150, a6 \n\t"
+ " \n\t"
+ " cmpi.l #10, d0 \n\t"
+ " bne reg_test_2_error \n\t"
+ " cmpi.l #20, d1 \n\t"
+ " bne reg_test_2_error \n\t"
+ " cmpi.l #30, d2 \n\t"
+ " bne reg_test_2_error \n\t"
+ " cmpi.l #40, d3 \n\t"
+ " bne reg_test_2_error \n\t"
+ " cmpi.l #50, d4 \n\t"
+ " bne reg_test_2_error \n\t"
+ " cmpi.l #60, d5 \n\t"
+ " bne reg_test_2_error \n\t"
+ " cmpi.l #70, d6 \n\t"
+ " bne reg_test_2_error \n\t"
+ " cmpi.l #80, d7 \n\t"
+ " bne reg_test_2_error \n\t"
+ " move a0, d0 \n\t"
+ " cmpi.l #90, d0 \n\t"
+ " bne reg_test_2_error \n\t"
+ " move a1, d0 \n\t"
+ " cmpi.l #100, d0 \n\t"
+ " bne reg_test_2_error \n\t"
+ " move a2, d0 \n\t"
+ " cmpi.l #110, d0 \n\t"
+ " bne reg_test_2_error \n\t"
+ " move a3, d0 \n\t"
+ " cmpi.l #120, d0 \n\t"
+ " bne reg_test_2_error \n\t"
+ " move a4, d0 \n\t"
+ " cmpi.l #130, d0 \n\t"
+ " bne reg_test_2_error \n\t"
+ " move a5, d0 \n\t"
+ " cmpi.l #140, d0 \n\t"
+ " bne reg_test_2_error \n\t"
+ " move a6, d0 \n\t"
+ " cmpi.l #150, d0 \n\t"
+ " bne reg_test_2_error \n\t"
+ " move ulRegTest1Counter, d0 \n\t"
+ " addq #1, d0 \n\t"
+ " move d0, ulRegTest2Counter \n\t"
+ " bra reg_test_2_start \n\t"
+ "reg_test_2_error: \n\t"
+ " bra reg_test_2_error \n\t"
+ );
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/printf-stdarg.c b/Demo/ColdFire_MCF52259_CodeWarrior/printf-stdarg.c new file mode 100644 index 00000000..f6139dc8 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/printf-stdarg.c @@ -0,0 +1,293 @@ +/*
+ Copyright 2001, 2002 Georges Menie (www.menie.org)
+ stdarg version contributed by Christian Ettinger
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+/*
+ putchar is the only external dependency for this file,
+ if you have a working putchar, leave it commented out.
+ If not, uncomment the define below and
+ replace outbyte(c) by your own function call.
+
+*/
+
+#define putchar(c) c
+
+#include <stdarg.h>
+
+static void printchar(char **str, int c)
+{
+ //extern int putchar(int c);
+
+ if (str) {
+ **str = (char)c;
+ ++(*str);
+ }
+ else
+ {
+ (void)putchar(c);
+ }
+}
+
+#define PAD_RIGHT 1
+#define PAD_ZERO 2
+
+static int prints(char **out, const char *string, int width, int pad)
+{
+ register int pc = 0, padchar = ' ';
+
+ if (width > 0) {
+ register int len = 0;
+ register const char *ptr;
+ for (ptr = string; *ptr; ++ptr) ++len;
+ if (len >= width) width = 0;
+ else width -= len;
+ if (pad & PAD_ZERO) padchar = '0';
+ }
+ if (!(pad & PAD_RIGHT)) {
+ for ( ; width > 0; --width) {
+ printchar (out, padchar);
+ ++pc;
+ }
+ }
+ for ( ; *string ; ++string) {
+ printchar (out, *string);
+ ++pc;
+ }
+ for ( ; width > 0; --width) {
+ printchar (out, padchar);
+ ++pc;
+ }
+
+ return pc;
+}
+
+/* the following should be enough for 32 bit int */
+#define PRINT_BUF_LEN 12
+
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)
+{
+ char print_buf[PRINT_BUF_LEN];
+ register char *s;
+ register int t, neg = 0, pc = 0;
+ register unsigned int u = (unsigned int)i;
+
+ if (i == 0) {
+ print_buf[0] = '0';
+ print_buf[1] = '\0';
+ return prints (out, print_buf, width, pad);
+ }
+
+ if (sg && b == 10 && i < 0) {
+ neg = 1;
+ u = (unsigned int)-i;
+ }
+
+ s = print_buf + PRINT_BUF_LEN-1;
+ *s = '\0';
+
+ while (u) {
+ t = (int)u % b;
+ if( t >= 10 )
+ t += letbase - '0' - 10;
+ *--s = (char)(t + '0');
+ u /= b;
+ }
+
+ if (neg) {
+ if( width && (pad & PAD_ZERO) ) {
+ printchar (out, '-');
+ ++pc;
+ --width;
+ }
+ else {
+ *--s = '-';
+ }
+ }
+
+ return pc + prints (out, s, width, pad);
+}
+
+static int print( char **out, const char *format, va_list args )
+{
+ register int width, pad;
+ register int pc = 0;
+ char scr[2];
+
+ for (; *format != 0; ++format) {
+ if (*format == '%') {
+ ++format;
+ width = pad = 0;
+ if (*format == '\0') break;
+ if (*format == '%') goto out;
+ if (*format == '-') {
+ ++format;
+ pad = PAD_RIGHT;
+ }
+ while (*format == '0') {
+ ++format;
+ pad |= PAD_ZERO;
+ }
+ for ( ; *format >= '0' && *format <= '9'; ++format) {
+ width *= 10;
+ width += *format - '0';
+ }
+ if( *format == 's' ) {
+ register char *s = (char *)va_arg( args, int );
+ pc += prints (out, s?s:"(null)", width, pad);
+ continue;
+ }
+ if( *format == 'd' ) {
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'x' ) {
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'X' ) {
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');
+ continue;
+ }
+ if( *format == 'u' ) {
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'c' ) {
+ /* char are converted to int then pushed on the stack */
+ scr[0] = (char)va_arg( args, int );
+ scr[1] = '\0';
+ pc += prints (out, scr, width, pad);
+ continue;
+ }
+ }
+ else {
+ out:
+ printchar (out, *format);
+ ++pc;
+ }
+ }
+ if (out) **out = '\0';
+ va_end( args );
+ return pc;
+}
+
+int printf(const char *format, ...)
+{
+ va_list args;
+
+ va_start( args, format );
+ return print( 0, format, args );
+}
+
+int sprintf(char *out, const char *format, ...)
+{
+ va_list args;
+
+ va_start( args, format );
+ return print( &out, format, args );
+}
+
+
+int snprintf( char *buf, unsigned int count, const char *format, ... )
+{
+ va_list args;
+
+ ( void ) count;
+
+ va_start( args, format );
+ return print( &buf, format, args );
+}
+
+
+#ifdef TEST_PRINTF
+int main(void)
+{
+ char *ptr = "Hello world!";
+ char *np = 0;
+ int i = 5;
+ unsigned int bs = sizeof(int)*8;
+ int mi;
+ char buf[80];
+
+ mi = (1 << (bs-1)) + 1;
+ printf("%s\n", ptr);
+ printf("printf test\n");
+ printf("%s is null pointer\n", np);
+ printf("%d = 5\n", i);
+ printf("%d = - max int\n", mi);
+ printf("char %c = 'a'\n", 'a');
+ printf("hex %x = ff\n", 0xff);
+ printf("hex %02x = 00\n", 0);
+ printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);
+ printf("%d %s(s)%", 0, "message");
+ printf("\n");
+ printf("%d %s(s) with %%\n", 0, "message");
+ sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);
+ sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);
+ sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);
+ sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);
+ sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);
+ sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);
+ sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);
+ sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);
+
+ return 0;
+}
+
+/*
+ * if you compile this file with
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c
+ * you will get a normal warning:
+ * printf.c:214: warning: spurious trailing `%' in format
+ * this line is testing an invalid % at the end of the format string.
+ *
+ * this should display (on 32bit int machine) :
+ *
+ * Hello world!
+ * printf test
+ * (null) is null pointer
+ * 5 = 5
+ * -2147483647 = - max int
+ * char a = 'a'
+ * hex ff = ff
+ * hex 00 = 00
+ * signed -3 = unsigned 4294967293 = hex fffffffd
+ * 0 message(s)
+ * 0 message(s) with %
+ * justif: "left "
+ * justif: " right"
+ * 3: 0003 zero padded
+ * 3: 3 left justif.
+ * 3: 3 right justif.
+ * -3: -003 zero padded
+ * -3: -3 left justif.
+ * -3: -3 right justif.
+ */
+
+#endif
+
+
+/* To keep linker happy. */
+int write( int i, char* c, int n)
+{
+ (void)i;
+ (void)n;
+ (void)c;
+ return 0;
+}
+
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/readme.txt b/Demo/ColdFire_MCF52259_CodeWarrior/readme.txt new file mode 100644 index 00000000..7076a79f --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/readme.txt @@ -0,0 +1,160 @@ +//------------------------------------------------------------------------
+// Readme.txt
+//------------------------------------------------------------------------
+This project is configure to get you up and running quickly using
+CodeWarrior with the Freescale MCF52259 board.
+
+This project provides full support for the selected board.
+The created project provides Standard IO Support through console and terminal window.
+
+Sample code for the following language:
+- C
+
+
+//------------------------------------------------------------------------
+// Memory Maps
+//------------------------------------------------------------------------
+The Hardware has the following memory map:
+
+# MCF52259 Derivative Memory map definitions from linker command files:
+# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
+# symbols must be defined in the linker command file.
+
+# Memory Mapped Registers (IPSBAR= 0x40000000)
+ ___IPSBAR = 0x40000000;
+
+# 32 Kbytes Internal SRAM
+ ___RAMBAR = 0x20000000;
+ ___RAMBAR_SIZE = 0x00008000;
+
+# 512 KByte Internal Flash Memory
+ ___FLASHBAR = 0x00000000;
+ ___FLASHBAR_SIZE = 0x00080000;
+
+
+
+//------------------------------------------------------------------------
+// Project Structure
+//------------------------------------------------------------------------
+The project generated contains various files/groups:
+- readme.txt: information for this project
+- Sources: application source codes, user customizable startup
+ code, uart library, exception table
+- Includes: derivative and board header files, ...
+- Libs: runtime and libs
+- Project Settings: linker command files for the different build
+ targets, the initialization and memory configuration files for
+ the hardware debugging, the common startup code, etc...
+
+//------------------------------------------------------------------------
+// Build Targets
+//------------------------------------------------------------------------
+- CONSOLE_INTERNAL_RAM:
+This project target is setup to load and debug code from internal RAM.
+It should be used during your application development.
+The application outputs to the CodeWarrior's console window.
+
+- INTERNAL_RAM:
+This project target is setup to load and debug code from internal RAM.
+It should be used during your application development.
+This is the very basic project that outputs to the UART.
+You needs to connect a Terminal Program to see the output.
+
+- INTERNAL_FLASH:
+This project target is setup to load and debug code in Internal FLASH.
+This is the very basic project that outputs to the UART. User needs
+to connect the terminal to see the output.
+
+
+
+===================================================================
+WARNING regarding debugging new project wizard code with CCS-SIM
+===================================================================
+The CCS-SIM is an instruction set simulator, it does not implement
+any peripherals.
+The new project generated by the wizard are using startup code
+performing some hardware peripheral initializations.
+When debugging with the CCS-SIM it might happen that the simulation
+stuck on loop using non implemented peripheral register flag as
+condition (PLL initialization as example).
+In this case, you should either:
+- move the PC to next statement
+- use a skip point
+- define a simulator specific macro which used when define allos you
+to comment out the unwanted code in order to debug with CCS-SIM
+
+
+===================================================================
+WARNING regarding code located in RAM
+===================================================================
+Many possible ColdFire target processors have an external bus, so
+you can use large external RAM devices for debugging applications
+during development. But some processors do not have an external
+bus, so you must accommodate applications in on-chip memory.
+Although this on-chip RAM accommodates this CodeWarrior project,
+it probably is too small for full development of your application.
+Accordingly, for a processor without external bus, you should locate
+your applications in flash memory.
+
+//------------------------------------------------------------------------
+// Flashing the code
+//------------------------------------------------------------------------
+1. Select the appropriate project target and build it
+2. Make sure the correct remote connection is selected in the Remote
+ Connection debugger panel
+3. In the CodeWarrior IDE menu, select Project > Set Default Project
+ and select your project
+4. In the CodeWarrior IDE menu, select Project > Set Default Target
+ and select the project target that has the code you want to flash
+5. In the CodeWarrior IDE menu, select Tools > Flash Programmer
+6. Go to the flash programmer Target Configuration panel, click Load
+ Settings
+7. Browse to the <your project location>\cfg sub folder and
+ select the flash settings xml file matching your build target
+8. Check that Use Custom Settings checkbox is not selected
+9. Go to the Erase/Blank Check panel, select the All Sectors option and
+ click Erase
+10. Go to Program/Verify panel, click Program
+11. Your code should now be flashed
+
+//------------------------------------------------------------------------
+// Terminal Settings
+//------------------------------------------------------------------------
+In case the UART is supported, the terminal should be setup with:
+- 19200 bauds,
+- 8 data bits,
+- no parity,
+- 1 stop bit,
+- no flow control.
+
+Please check this file in the project.
+
+//------------------------------------------------------------------------
+// Getting Started
+//------------------------------------------------------------------------
+To build/debug your project, use the CodeWarrior IDE menu Project > Debug
+or press F5. This will launch the debugger. Press again F5 in the
+debugger (or the CodeWarrior IDE menu Project > Run) to start the
+application. The CodeWarrior IDE menu Project > Break stops the
+application.
+
+//------------------------------------------------------------------------
+// Adding your own code
+//------------------------------------------------------------------------
+Once everything is working as expected, you can begin adding your own code
+to the project. Keep in mind that we provide this as an example of how to
+get up and running quickly with CodeWarrior. There are certainly other
+ways to handle interrupts and set up your linker command file. Feel free
+to modify any of the source files provided.
+
+//------------------------------------------------------------------------
+// Additional documentation
+//------------------------------------------------------------------------
+Read the online documentation provided. In CodeWarrior IDE menu, select
+Help > CodeWarrior Help.
+
+//------------------------------------------------------------------------
+// Contacting Freescale
+//------------------------------------------------------------------------
+For bug reports, technical questions, and suggestions, please use the
+forms installed in the Release_Notes folder.
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/stdlib.c b/Demo/ColdFire_MCF52259_CodeWarrior/stdlib.c new file mode 100644 index 00000000..5e364659 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/stdlib.c @@ -0,0 +1,479 @@ +/* FILENAME: stdlib.c
+ *
+ * Functions normally found in a standard C lib.
+ *
+ * 12/28/2005 - added memcmp and memmove
+ *
+ * Notes: These functions support ASCII only!!!
+ */
+
+#include "common.h"
+#include "stdlib.h"
+
+/****************************************************************/
+int
+isspace (int ch)
+{
+ if ((ch == ' ') || (ch == '\t')) /* \n ??? */
+ return TRUE;
+ else
+ return FALSE;
+}
+
+/****************************************************************/
+int
+isalnum (int ch)
+{
+ /* ASCII only */
+ if (((ch >= '0') && (ch <= '9')) ||
+ ((ch >= 'A') && (ch <= 'Z')) ||
+ ((ch >= 'a') && (ch <= 'z')))
+ return TRUE;
+ else
+ return FALSE;
+}
+
+/****************************************************************/
+int
+isdigit (int ch)
+{
+ /* ASCII only */
+ if ((ch >= '0') && (ch <= '9'))
+ return TRUE;
+ else
+ return FALSE;
+}
+
+/****************************************************************/
+int
+isupper (int ch)
+{
+ /* ASCII only */
+ if ((ch >= 'A') && (ch <= 'Z'))
+ return TRUE;
+ else
+ return FALSE;
+}
+
+/****************************************************************/
+int
+strcasecmp (const char *s1, const char *s2)
+{
+ char c1, c2;
+ int result = 0;
+
+ while (result == 0)
+ {
+ c1 = *s1++;
+ c2 = *s2++;
+ if ((c1 >= 'a') && (c1 <= 'z'))
+ c1 = (char)(c1 - ' ');
+ if ((c2 >= 'a') && (c2 <= 'z'))
+ c2 = (char)(c2 - ' ');
+ if ((result = (c1 - c2)) != 0)
+ break;
+ if ((c1 == 0) || (c2 == 0))
+ break;
+ }
+ return result;
+}
+
+
+/****************************************************************/
+int
+stricmp (const char *s1, const char *s2)
+{
+ return (strcasecmp(s1, s2));
+}
+
+/****************************************************************/
+int
+strncasecmp (const char *s1, const char *s2, int n)
+{
+ char c1, c2;
+ int k = 0;
+ int result = 0;
+
+ while ( k++ < n )
+ {
+ c1 = *s1++;
+ c2 = *s2++;
+ if ((c1 >= 'a') && (c1 <= 'z'))
+ c1 = (char)(c1 - ' ');
+ if ((c2 >= 'a') && (c2 <= 'z'))
+ c2 = (char)(c2 - ' ');
+ if ((result = (c1 - c2)) != 0)
+ break;
+ if ((c1 == 0) || (c2 == 0))
+ break;
+ }
+ return result;
+}
+
+/****************************************************************/
+int
+strnicmp (const char *s1, const char *s2, int n)
+{
+ return (strncasecmp(s1, s2, n));
+}
+
+/****************************************************************/
+uint32
+strtoul (char *str, char **ptr, int base)
+{
+ unsigned long rvalue = 0;
+ int neg = 0;
+ int c;
+
+ /* Validate parameters */
+ if ((str != NULL) && (base >= 0) && (base <= 36))
+ {
+ /* Skip leading white spaces */
+ while (isspace(*str))
+ {
+ ++str;
+ }
+
+ /* Check for notations */
+ switch (str[0])
+ {
+ case '0':
+ if (base == 0)
+ {
+ if ((str[1] == 'x') || (str[1] == 'X'))
+ {
+ base = 16;
+ str += 2;
+ }
+ else
+ {
+ base = 8;
+ str++;
+ }
+ }
+ break;
+
+ case '-':
+ neg = 1;
+ str++;
+ break;
+
+ case '+':
+ str++;
+ break;
+
+ default:
+ break;
+ }
+
+ if (base == 0)
+ base = 10;
+
+ /* Valid "digits" are 0..9, A..Z, a..z */
+ while (isalnum(c = *str))
+ {
+ /* Convert char to num in 0..36 */
+ if ((c -= ('a' - 10)) < 10) /* 'a'..'z' */
+ {
+ if ((c += ('a' - 'A')) < 10) /* 'A'..'Z' */
+ {
+ c += ('A' - '0' - 10); /* '0'..'9' */
+ }
+ }
+
+ /* check c against base */
+ if (c >= base)
+ {
+ break;
+ }
+
+ if (neg)
+ {
+ rvalue = (rvalue * base) - c;
+ }
+ else
+ {
+ rvalue = (rvalue * base) + c;
+ }
+
+ ++str;
+ }
+ }
+
+ /* Upon exit, 'str' points to the character at which valid info */
+ /* STOPS. No chars including and beyond 'str' are used. */
+
+ if (ptr != NULL)
+ *ptr = str;
+
+ return rvalue;
+ }
+
+/****************************************************************/
+int
+atoi (const char *str)
+{
+ char *s = (char *)str;
+
+ return ((int)strtoul(s, NULL, 10));
+}
+
+/****************************************************************/
+int
+strlen (const char *str)
+{
+ char *s = (char *)str;
+ int len = 0;
+
+ if (s == NULL)
+ return 0;
+
+ while (*s++ != '\0')
+ ++len;
+
+ return len;
+}
+
+/****************************************************************/
+char *
+strcat (char *dest, const char *src)
+{
+ char *dp;
+ char *sp = (char *)src;
+
+ if ((dest != NULL) && (src != NULL))
+ {
+ dp = &dest[strlen(dest)];
+
+ while (*sp != '\0')
+ {
+ *dp++ = *sp++;
+ }
+ *dp = '\0';
+ }
+ return dest;
+}
+
+/****************************************************************/
+char *
+strncat (char *dest, const char *src, int n)
+{
+ char *dp;
+ char *sp = (char *)src;
+
+ if ((dest != NULL) && (src != NULL) && (n > 0))
+ {
+ dp = &dest[strlen(dest)];
+
+ while ((*sp != '\0') && (n-- > 0))
+ {
+ *dp++ = *sp++;
+ }
+ *dp = '\0';
+ }
+ return dest;
+}
+
+/****************************************************************/
+char *
+strcpy (char *dest, const char *src)
+{
+ char *dp = (char *)dest;
+ char *sp = (char *)src;
+
+ if ((dest != NULL) && (src != NULL))
+ {
+ while (*sp != '\0')
+ {
+ *dp++ = *sp++;
+ }
+ *dp = '\0';
+ }
+ return dest;
+}
+
+/****************************************************************/
+char *
+strncpy (char *dest, const char *src, int n)
+{
+ char *dp = (char *)dest;
+ char *sp = (char *)src;
+
+ if ((dest != NULL) && (src != NULL) && (n > 0))
+ {
+ while ((*sp != '\0') && (n-- > 0))
+ {
+ *dp++ = *sp++;
+ }
+ *dp = '\0';
+ }
+ return dest;
+}
+
+/****************************************************************/
+int
+strcmp (const char *s1, const char *s2)
+{
+ /* No checks for NULL */
+ char *s1p = (char *)s1;
+ char *s2p = (char *)s2;
+
+ while (*s2p != '\0')
+ {
+ if (*s1p != *s2p)
+ break;
+
+ ++s1p;
+ ++s2p;
+ }
+ return (*s1p - *s2p);
+}
+
+/****************************************************************/
+int
+strncmp (const char *s1, const char *s2, int n)
+{
+ /* No checks for NULL */
+ char *s1p = (char *)s1;
+ char *s2p = (char *)s2;
+
+ if (n <= 0)
+ return 0;
+
+ while (*s2p != '\0')
+ {
+ if (*s1p != *s2p)
+ break;
+
+ if (--n == 0)
+ break;
+
+ ++s1p;
+ ++s2p;
+ }
+ return (*s1p - *s2p);
+}
+
+/****************************************************************/
+char *
+strstr(const char *s1, const char *s2)
+{
+ char *sp = (char *)s1;
+ int len1 = strlen(s1);
+ int len2 = strlen(s2);
+
+ while (len1 >= len2)
+ {
+ if (strncmp(sp, s2, len2) == 0)
+ {
+ return (sp);
+ }
+ ++sp;
+ --len1;
+ }
+
+ return (NULL);
+}
+
+/****************************************************************/
+char *
+strchr(const char *str, int c)
+{
+ char *sp = (char *)str;
+ char ch = (char)(c & 0xff);
+
+ while (*sp != '\0')
+ {
+ if (*sp == ch)
+ {
+ return (sp);
+ }
+ ++sp;
+ }
+
+ return (NULL);
+}
+
+/****************************************************************/
+void *
+memcpy (void *dest, const void *src, unsigned n)
+{
+ unsigned char *dbp = (unsigned char *)dest;
+ unsigned char *sbp = (unsigned char *)src;
+
+ if ((dest != NULL) && (src != NULL) && (n > 0))
+ {
+ while (n--)
+ *dbp++ = *sbp++;
+ }
+ return dest;
+}
+
+/****************************************************************/
+void *
+memset (void *s, int c, unsigned n)
+{
+ /* Not optimized, but very portable */
+ unsigned char *sp = (unsigned char *)s;
+
+ if ((s != NULL) && (n > 0))
+ {
+ while (n--)
+ {
+ *sp++ = (unsigned char)c;
+ }
+ }
+ return s;
+}
+
+/****************************************************************/
+int
+memcmp (const void *s1, const void *s2, unsigned n)
+{
+ unsigned char *s1p, *s2p;
+
+ if (s1 && s2 && (n > 0))
+ {
+ s1p = (unsigned char *)s1;
+ s2p = (unsigned char *)s2;
+
+ while ((--n >= 0) && (*s1p == *s2p))
+ {
+ if (*s1p != *s2p)
+ return (*s1p - *s2p);
+ ++s1p;
+ ++s2p;
+ }
+ }
+
+ return (0);
+}
+
+/****************************************************************/
+void *
+memmove (void *dest, const void *src, unsigned n)
+{
+ unsigned char *dbp = (unsigned char *)dest;
+ unsigned char *sbp = (unsigned char *)src;
+ unsigned char *dend = dbp + n;
+ unsigned char *send = sbp + n;
+
+ if ((dest != NULL) && (src != NULL) && (n > 0))
+ {
+ /* see if a memcpy would overwrite source buffer */
+ if ((sbp < dbp) && (dbp < send))
+ {
+ while (n--)
+ *(--dend) = *(--send);
+ }
+ else
+ {
+ while (n--)
+ *dbp++ = *sbp++;
+ }
+ }
+
+ return dest;
+}
+
+/****************************************************************/
diff --git a/Demo/ColdFire_MCF52259_CodeWarrior/stdlib.h b/Demo/ColdFire_MCF52259_CodeWarrior/stdlib.h new file mode 100644 index 00000000..7a9865d9 --- /dev/null +++ b/Demo/ColdFire_MCF52259_CodeWarrior/stdlib.h @@ -0,0 +1,79 @@ +/*
+ * File: stdlib.h
+ * Purpose: Function prototypes for standard library functions
+ *
+ * Notes:
+ */
+
+#ifndef _STDLIB_H
+#define _STDLIB_H
+
+/********************************************************************
+ * Standard library functions
+ ********************************************************************/
+
+int
+isspace (int);
+
+int
+isalnum (int);
+
+int
+isdigit (int);
+
+int
+isupper (int);
+
+int
+strcasecmp (const char *, const char *);
+
+int
+strncasecmp (const char *, const char *, int);
+
+unsigned long
+strtoul (char *, char **, int);
+
+int
+strlen (const char *);
+
+char *
+strcat (char *, const char *);
+
+char *
+strncat (char *, const char *, int);
+
+char *
+strcpy (char *, const char *);
+
+char *
+strncpy (char *, const char *, int);
+
+int
+strcmp (const char *, const char *);
+
+int
+strncmp (const char *, const char *, int);
+
+void *
+memcpy (void *, const void *, unsigned);
+
+void *
+memset (void *, int, unsigned);
+
+void
+free (void *);
+
+void *
+malloc (unsigned);
+
+#define RAND_MAX 32767
+
+int
+rand (void);
+
+void
+srand (int);
+
+/********************************************************************/
+
+#endif
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