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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2011-05-29 03:58:16 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2011-05-29 03:58:16 +0000 |
| commit | 03dc1868d15f6113e93827e7812d817a3ec2ec3a (patch) | |
| tree | a97e5aa6b33f29ce8db6435ada0f211f120e65a4 | |
| parent | 11fd5c0cd989010a2dfa59c75e3d5a5d2a970300 (diff) | |
| download | llvm-03dc1868d15f6113e93827e7812d817a3ec2ec3a.tar.gz llvm-03dc1868d15f6113e93827e7812d817a3ec2ec3a.tar.bz2 llvm-03dc1868d15f6113e93827e7812d817a3ec2ec3a.tar.xz | |
Fix to match the dwarf register numbers that gdb uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132278 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index 5ef4daed2f..c1ef2e7e28 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -117,22 +117,22 @@ def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; // Aliases of the F* registers used to hold 64-bit fp values (doubles) -def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>; -def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>; -def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>; -def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>; -def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>; -def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[42]>; -def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[44]>; -def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[46]>; -def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[48]>; -def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[50]>; -def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[52]>; -def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[54]>; -def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[56]>; -def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[58]>; -def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[60]>; -def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[62]>; +def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>; +def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>; +def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>; +def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>; +def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>; +def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>; +def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>; +def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>; +def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>; +def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>; +def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>; +def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>; +def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>; +def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>; +def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>; +def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>; // Register classes. // |