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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-10-23 00:44:19 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-10-23 00:44:19 +0000 |
| commit | 6a2f9b91379140c36a11ade6c0673bd7490eba32 (patch) | |
| tree | b18920c632ff2b48e61d4d752f128d35f220963b | |
| parent | f9e5c398119a77202dc0f7861f5131a7b9f7b8b3 (diff) | |
| download | llvm-6a2f9b91379140c36a11ade6c0673bd7490eba32.tar.gz llvm-6a2f9b91379140c36a11ade6c0673bd7490eba32.tar.bz2 llvm-6a2f9b91379140c36a11ade6c0673bd7490eba32.tar.xz | |
R600/SI: Add support for i64 bitwise or
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193213 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 19 | ||||
| -rw-r--r-- | test/CodeGen/R600/or.ll | 21 |
2 files changed, 36 insertions, 4 deletions
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 08a8b56fdc..ab6193fa4c 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1963,6 +1963,25 @@ def : Pat< >; //============================================================================// +// Miscellaneous Patterns +//===----------------------------------------------------------------------===// + +def : Pat < + (i64 (trunc i128:$x)), + (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (i32 (EXTRACT_SUBREG $x, sub0)), sub0), + (i32 (EXTRACT_SUBREG $x, sub1)), sub1) +>; + +def : Pat < + (or i64:$a, i64:$b), + (INSERT_SUBREG + (INSERT_SUBREG (IMPLICIT_DEF), + (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub0), (EXTRACT_SUBREG $b, sub0)), sub0), + (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub1), (EXTRACT_SUBREG $b, sub1)), sub1) +>; + +//============================================================================// // Miscellaneous Optimization Patterns //============================================================================// diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll index 3db892a362..6950ed0dfb 100644 --- a/test/CodeGen/R600/or.ll +++ b/test/CodeGen/R600/or.ll @@ -1,11 +1,11 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; EG-CHECK: @or_v2i32 +; EG-CHECK-LABEL: @or_v2i32 ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @or_v2i32 +;SI-CHECK-LABEL: @or_v2i32 ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} @@ -18,13 +18,13 @@ define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) ret void } -; EG-CHECK: @or_v4i32 +; EG-CHECK-LABEL: @or_v4i32 ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @or_v4i32 +;SI-CHECK-LABEL: @or_v4i32 ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} @@ -38,3 +38,16 @@ define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } + +; EG-CHECK-LABEL: @or_i64 +; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y +; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[3].X +; SI-CHECK-LABEL: @or_i64 +; SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]}} +; SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]}} +define void @or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = or i64 %a, %b + store i64 %0, i64 addrspace(1)* %out + ret void +} |