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author | Quentin Colombet <qcolombet@apple.com> | 2013-12-12 00:15:47 +0000 |
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committer | Quentin Colombet <qcolombet@apple.com> | 2013-12-12 00:15:47 +0000 |
commit | b0f8afd43c54b9b5cb39eb1740eb1fedc4e6471c (patch) | |
tree | 0d26ede7f60c7b13cdf63b2080c93f2c92aa6f4a /include/llvm/CodeGen/ScheduleDAG.h | |
parent | 76eb77dd52c4ec215e79e25992f04e3095afe5df (diff) | |
download | llvm-b0f8afd43c54b9b5cb39eb1740eb1fedc4e6471c.tar.gz llvm-b0f8afd43c54b9b5cb39eb1740eb1fedc4e6471c.tar.bz2 llvm-b0f8afd43c54b9b5cb39eb1740eb1fedc4e6471c.tar.xz |
Fix an over-constrained assertion in MachineFunction::addLiveIn.
The assertion was checking that the virtual register VReg used to represent the
physical register PReg uses the same register class as the one passed to
MachineFunction::addLiveIn.
This is over-constraining because it is sufficient to check that the register
class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and
that VRegRC contains PReg.
Indeed, if VReg gets constrained because of some operation constraints
between two calls of MachineFunction::addLiveIn, the original assertion
cannot match.
This fixes <rdar://problem/15633429>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197097 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/ScheduleDAG.h')
0 files changed, 0 insertions, 0 deletions