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| author | Tim Northover <tnorthover@apple.com> | 2014-03-31 15:46:22 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-03-31 15:46:22 +0000 |
| commit | 13277a78bc30f09e9f917850a01fc929aa16eaae (patch) | |
| tree | 86637bb3b9d865284121e8039845fc7491c67d77 /include/llvm/IR | |
| parent | 8f93e159ededcdcd76e7b328d249b008528f1e56 (diff) | |
| download | llvm-13277a78bc30f09e9f917850a01fc929aa16eaae.tar.gz llvm-13277a78bc30f09e9f917850a01fc929aa16eaae.tar.bz2 llvm-13277a78bc30f09e9f917850a01fc929aa16eaae.tar.xz | |
ARM64: add more scalar patterns for reciprocal ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205203 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/IR')
| -rw-r--r-- | include/llvm/IR/IntrinsicsARM64.td | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/include/llvm/IR/IntrinsicsARM64.td b/include/llvm/IR/IntrinsicsARM64.td index 56f1b1de3d..b280d005d0 100644 --- a/include/llvm/IR/IntrinsicsARM64.td +++ b/include/llvm/IR/IntrinsicsARM64.td @@ -268,6 +268,9 @@ let Properties = [IntrNoMem] in { def int_arm64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic; def int_arm64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic; + // Reciprocal Exponent + def int_arm64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic; + // Vector Saturating Shift Left def int_arm64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic; def int_arm64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic; @@ -339,11 +342,11 @@ let Properties = [IntrNoMem] in { // Vector Reciprocal Estimate def int_arm64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic; - def int_arm64_neon_frecpe : AdvSIMD_1VectorArg_Intrinsic; + def int_arm64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic; // Vector Square Root Estimate def int_arm64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic; - def int_arm64_neon_frsqrte : AdvSIMD_1VectorArg_Intrinsic; + def int_arm64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic; // Vector Bitwise Reverse def int_arm64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic; |