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| author | Owen Anderson <resistor@mac.com> | 2012-05-24 21:37:08 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2012-05-24 21:37:08 +0000 |
| commit | 6b31d4ea3610b04d71e1eb38d8fc625eae7b759a (patch) | |
| tree | 5a8152caa3dd148168f29df834b539b98136d5bb /include/llvm/Target/Target.td | |
| parent | d6d05e3f788d60d5c76ab99ce95ea6f622932d90 (diff) | |
| download | llvm-6b31d4ea3610b04d71e1eb38d8fc625eae7b759a.tar.gz llvm-6b31d4ea3610b04d71e1eb38d8fc625eae7b759a.tar.bz2 llvm-6b31d4ea3610b04d71e1eb38d8fc625eae7b759a.tar.xz | |
Teach tblgen's set theory "sequence" operator to support an optional stride operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157416 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target/Target.td')
| -rw-r--r-- | include/llvm/Target/Target.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 1f2bd470b7..e053ce8c6b 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -191,7 +191,8 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, // also in the second set. // // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of -// numbered registers. +// numbered registers. Takes an optional 4th operand which is a stride to use +// when generating the sequence. // // (shl GPR, 4) - Remove the first N elements. // |