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-rw-r--r--include/llvm/Target/Target.td3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 1f2bd470b7..e053ce8c6b 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -191,7 +191,8 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
// also in the second set.
//
// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
-// numbered registers.
+// numbered registers. Takes an optional 4th operand which is a stride to use
+// when generating the sequence.
//
// (shl GPR, 4) - Remove the first N elements.
//