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author | Michael Zolotukhin <mzolotukhin@apple.com> | 2014-04-21 12:01:33 +0000 |
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committer | Michael Zolotukhin <mzolotukhin@apple.com> | 2014-04-21 12:01:33 +0000 |
commit | d329c79f164b5bd876014c4c0225ae298640bd81 (patch) | |
tree | ded4f1ac6e6abb0f9b92781c0df2ef5f55ef1610 /include/llvm | |
parent | acbc9cb577e816c57c37c95b7dddb4cad835b0ba (diff) | |
download | llvm-d329c79f164b5bd876014c4c0225ae298640bd81.tar.gz llvm-d329c79f164b5bd876014c4c0225ae298640bd81.tar.bz2 llvm-d329c79f164b5bd876014c4c0225ae298640bd81.tar.xz |
Reapply r206732. This time without optimization of branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206749 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm')
-rw-r--r-- | include/llvm/IR/Intrinsics.td | 13 | ||||
-rw-r--r-- | include/llvm/Target/TargetLowering.h | 16 |
2 files changed, 29 insertions, 0 deletions
diff --git a/include/llvm/IR/Intrinsics.td b/include/llvm/IR/Intrinsics.td index 6a48f17393..c65b86f5b7 100644 --- a/include/llvm/IR/Intrinsics.td +++ b/include/llvm/IR/Intrinsics.td @@ -444,6 +444,19 @@ def int_umul_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; +def int_safe_udiv : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], + [LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem]>; +def int_safe_urem : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], + [LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem]>; +def int_safe_sdiv : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], + [LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem]>; +def int_safe_srem : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], + [LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem]>; + //===------------------------- Memory Use Markers -------------------------===// // def int_lifetime_start : Intrinsic<[], diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 5afcd80a28..2e4956f16d 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -218,6 +218,10 @@ public: /// Return true if pow2 div is cheaper than a chain of srl/add/sra. bool isPow2DivCheap() const { return Pow2DivIsCheap; } + /// Return true if Div never traps, returns 0 when div by 0 and return TMin, + /// when sdiv TMin by -1. + bool isDivWellDefined() const { return DivIsWellDefined; } + /// Return true if Flow Control is an expensive operation that should be /// avoided. bool isJumpExpensive() const { return JumpIsExpensive; } @@ -1026,6 +1030,13 @@ protected: /// signed divide by power of two, and let the target handle it. void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } + /// Tells the code-generator that it is safe to execute sdiv/udiv/srem/urem + /// even when RHS is 0. It is also safe to execute sdiv/srem when LHS is + /// SignedMinValue and RHS is -1. + void setDivIsWellDefined (bool isWellDefined = true) { + DivIsWellDefined = isWellDefined; + } + /// Add the specified register class as an available regclass for the /// specified value type. This indicates the selector can handle values of /// that class natively. @@ -1441,6 +1452,11 @@ private: /// signed divide by power of two, and let the target handle it. bool Pow2DivIsCheap; + /// Tells the code-generator that it is safe to execute sdiv/udiv/srem/urem + /// even when RHS is 0. It is also safe to execute sdiv/srem when LHS is + /// SignedMinValue and RHS is -1. + bool DivIsWellDefined; + /// Tells the code generator that it shouldn't generate extra flow control /// instructions and should attempt to combine flow control instructions via /// predication. |