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| author | Alp Toker <alp@nuanti.com> | 2014-02-25 04:21:15 +0000 |
|---|---|---|
| committer | Alp Toker <alp@nuanti.com> | 2014-02-25 04:21:15 +0000 |
| commit | bf930d5c1fce8103d7a047d10d1a4543f28a4dd8 (patch) | |
| tree | 26755a27ad02049ce66d956d41a6c4c6600d8cda /lib/CodeGen/RegAllocGreedy.cpp | |
| parent | eb1b5ba880cbbc5aab1064c2ad0a95c8ca253de8 (diff) | |
| download | llvm-bf930d5c1fce8103d7a047d10d1a4543f28a4dd8.tar.gz llvm-bf930d5c1fce8103d7a047d10d1a4543f28a4dd8.tar.bz2 llvm-bf930d5c1fce8103d7a047d10d1a4543f28a4dd8.tar.xz | |
Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202107 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocGreedy.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocGreedy.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index 3c3f622759..21e23df107 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -1916,7 +1916,7 @@ RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, /// R3 is available. /// Recoloring => vC = R1, vA = R2, vB = R3 /// -/// \p Order defines the prefered allocation order for \p VirtReg. +/// \p Order defines the preferred allocation order for \p VirtReg. /// \p NewRegs will contain any new virtual register that have been created /// (split, spill) during the process and that must be assigned. /// \p FixedRegisters contains all the virtual registers that cannot be |