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| author | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2014-06-10 13:11:35 +0000 |
|---|---|---|
| committer | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2014-06-10 13:11:35 +0000 |
| commit | 45a31492d5475a1744966a0cd5e631694b29f953 (patch) | |
| tree | 1de64d9289e04769ccf7bf00324df191e33f9634 /lib/Target/AArch64/AArch64InstrFormats.td | |
| parent | 8316a97e024de3b335386922a6c3b6e1a7b197f5 (diff) | |
| download | llvm-45a31492d5475a1744966a0cd5e631694b29f953.tar.gz llvm-45a31492d5475a1744966a0cd5e631694b29f953.tar.bz2 llvm-45a31492d5475a1744966a0cd5e631694b29f953.tar.xz | |
Condition codes AL and NV are invalid in the aliases that use
inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).
Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.
The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210528 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64InstrFormats.td')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrFormats.td | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 42326fc182..446149b4fb 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -963,8 +963,14 @@ def ccode : Operand<i32> { let ParserMatchClass = CondCode; } def inv_ccode : Operand<i32> { + // AL and NV are invalid in the aliases which use inv_ccode let PrintMethod = "printInverseCondCode"; let ParserMatchClass = CondCode; + let MCOperandPredicate = [{ + return MCOp.isImm() && + MCOp.getImm() != AArch64CC::AL && + MCOp.getImm() != AArch64CC::NV; + }]; } // Conditional branch target. 19-bit immediate. The low two bits of the target |