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| author | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2014-06-09 11:10:14 +0000 |
|---|---|---|
| committer | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2014-06-09 11:10:14 +0000 |
| commit | a8d18fe94687b65f136b7222c2cc998c2148e39c (patch) | |
| tree | e7892cb480efb94475616c0d2284002a65164460 /lib/Target/AArch64/AArch64InstrFormats.td | |
| parent | 503447efbacbb69b9aa2401f53286ed9e027c42b (diff) | |
| download | llvm-a8d18fe94687b65f136b7222c2cc998c2148e39c.tar.gz llvm-a8d18fe94687b65f136b7222c2cc998c2148e39c.tar.bz2 llvm-a8d18fe94687b65f136b7222c2cc998c2148e39c.tar.xz | |
[AArch64] Missing aliases for CMP/CMN [W]SP with no shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210464 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64InstrFormats.td')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrFormats.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 4091c76fd4..42326fc182 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -1738,6 +1738,10 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> { WZR, GPR32:$src1, GPR32:$src2, 0), 5>; def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs") XZR, GPR64:$src1, GPR64:$src2, 0), 5>; + def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrx") + WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>; + def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrx64") + XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>; // Register/register aliases with no shift when SP is not used. def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"), |