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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-27 23:58:52 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-27 23:58:52 +0000 |
| commit | dd364419ee64cd5bb234af006ce0cb285e4a84ca (patch) | |
| tree | 39b3a87aca20346bf316390cb68c42812ce683ab /lib/Target/ARM/ARMBaseRegisterInfo.cpp | |
| parent | 94a935f072452d00207b1e8c1da75c31bb2a5f9b (diff) | |
| download | llvm-dd364419ee64cd5bb234af006ce0cb285e4a84ca.tar.gz llvm-dd364419ee64cd5bb234af006ce0cb285e4a84ca.tar.bz2 llvm-dd364419ee64cd5bb234af006ce0cb285e4a84ca.tar.xz | |
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.
Atomic loads are also prevented from participating in rematerialization
and load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 9deb96ea9e..828e7d4e95 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -870,10 +870,14 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { // return false for everything else. unsigned Opc = MI->getOpcode(); switch (Opc) { - case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: + case ARM::LDRi12: case ARM::ATOMIC_LDRi12: + case ARM::LDRH: case ARM::ATOMIC_LDRH: + case ARM::LDRBi12: case ARM::ATOMIC_LDRBi12: case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: - case ARM::t2LDRi12: case ARM::t2LDRi8: - case ARM::t2STRi12: case ARM::t2STRi8: + case ARM::t2LDRi12: case ARM::ATOMIC_t2LDRi12: + case ARM::t2LDRi8: case ARM::ATOMIC_t2LDRi8: + case ARM::t2STRi12: + case ARM::t2STRi8: case ARM::VLDRS: case ARM::VLDRD: case ARM::VSTRS: case ARM::VSTRD: case ARM::tSTRspi: case ARM::tLDRspi: |