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authorJim Grosbach <grosbach@apple.com>2011-08-17 21:51:27 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-17 21:51:27 +0000
commit70939ee1415722d7f39f13faf9b3644b96007996 (patch)
tree2c6a128afc34d663ef08f93901253692885d8fb1 /lib/Target/ARM/ARMCodeEmitter.cpp
parent795cf5efba4255cadd0bfde0e9d3dec65e96dd50 (diff)
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ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMCodeEmitter.cpp')
-rw-r--r--lib/Target/ARM/ARMCodeEmitter.cpp2
1 files changed, 0 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index c30aa37454..7d4eb6f18f 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -236,8 +236,6 @@ namespace {
const {return 0; }
uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
const { return 0; }
- unsigned getThumbSRImmOpValue(const MachineInstr &MI, unsigned OpIdx)
- const { return 0; }
unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
const {