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| author | Weiming Zhao <weimingz@codeaurora.org> | 2013-12-18 22:25:17 +0000 |
|---|---|---|
| committer | Weiming Zhao <weimingz@codeaurora.org> | 2013-12-18 22:25:17 +0000 |
| commit | 4fdb649f3aa05e7b25dab499af39d623e84acafe (patch) | |
| tree | d7cdf09e73d8c4da5ea76ecfd3354fde7baed7b4 /lib/Target/ARM | |
| parent | 5112542840c5be96f2245a2a0fa59dea57dfe6f4 (diff) | |
| download | llvm-4fdb649f3aa05e7b25dab499af39d623e84acafe.tar.gz llvm-4fdb649f3aa05e7b25dab499af39d623e84acafe.tar.bz2 llvm-4fdb649f3aa05e7b25dab499af39d623e84acafe.tar.xz | |
[aarch32] fix bug 18268: Incorrect condition of vsel
Given vsel_cc, op1, op2, since vsel has no LE/LT, to generate vsel for
such selection, it needs to inverse cc and swap op1 and op2. To inverse
cc, both L/G and E bits should be flipped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197615 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 9bdec10a64..017c86667e 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -3232,7 +3232,7 @@ SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) { if (CC == ISD::SETNE) return ISD::SETEQ; - return ISD::getSetCCSwappedOperands(CC); + return ISD::getSetCCInverse(CC, true); } static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, |