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| author | Andrew Lenharth <andrewl@lenharth.org> | 2006-04-02 21:08:39 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-04-02 21:08:39 +0000 |
| commit | ccd9f98bcb639a65146a5a969dae103017b81ab6 (patch) | |
| tree | 39f6587d02261042d5554677727112debedfe61b /lib/Target/Alpha/AlphaISelLowering.cpp | |
| parent | ed5d1afffb08bc389a0ae4e5c7382dee4d6f6f10 (diff) | |
| download | llvm-ccd9f98bcb639a65146a5a969dae103017b81ab6.tar.gz llvm-ccd9f98bcb639a65146a5a969dae103017b81ab6.tar.bz2 llvm-ccd9f98bcb639a65146a5a969dae103017b81ab6.tar.xz | |
This makes McCat/12-IOtest go 8x faster or so
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27363 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelLowering.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 3eb38e6451..b1111a6a82 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -585,10 +585,22 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); } - case ISD::SDIV: - case ISD::UDIV: case ISD::UREM: case ISD::SREM: + //Expand only on constant case + if (Op.getOperand(1).getOpcode() == ISD::Constant) { + MVT::ValueType VT = Op.Val->getValueType(0); + unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; + SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ? + BuildUDIVSequence(Op, &DAG) : + BuildSDIVSequence(Op, &DAG); + Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1)); + Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1); + return Tmp1; + } + //fall through + case ISD::SDIV: + case ISD::UDIV: if (MVT::isInteger(Op.getValueType())) { const char* opstr = 0; switch(Op.getOpcode()) { |