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| author | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
|---|---|---|
| committer | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
| commit | c23197a26f34f559ea9797de51e187087c039c42 (patch) | |
| tree | bf497ec9a02cd2fc0b64e3e58eff037a719a854d /lib/Target/Alpha/AlphaInstrInfo.cpp | |
| parent | 1f316e321a8f2fa0e193c5444584a67a8aabe9a8 (diff) | |
| download | llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.gz llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.bz2 llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.xz | |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 139a4db655..3cb2ce3720 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -201,7 +201,7 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); } void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::STQ; else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); @@ -246,7 +246,7 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); } void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -261,7 +261,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::LDQ; else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); @@ -332,7 +332,7 @@ static unsigned AlphaRevCondCode(unsigned Opcode) { case Alpha::FBLE: return Alpha::FBGT; case Alpha::FBLT: return Alpha::FBGE; default: - LLVM_UNREACHABLE("Unknown opcode"); + llvm_unreachable("Unknown opcode"); } return 0; // Not reached } |