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author | Chris Lattner <sabre@nondot.org> | 2006-05-04 17:21:20 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-05-04 17:21:20 +0000 |
commit | 63b3d7113d93fda622c4954c6b1d046ce029044e (patch) | |
tree | a1e0a659d24e6615f29a8184a3ae0b23ef6e6e03 /lib/Target/Alpha | |
parent | ceb408f6a263e319683209ae5c6f8d1e3e4d9b69 (diff) | |
download | llvm-63b3d7113d93fda622c4954c6b1d046ce029044e.tar.gz llvm-63b3d7113d93fda622c4954c6b1d046ce029044e.tar.bz2 llvm-63b3d7113d93fda622c4954c6b1d046ce029044e.tar.xz |
There shalt be only one "immediate" operand type!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28099 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha')
-rw-r--r-- | lib/Target/Alpha/AlphaAsmPrinter.cpp | 3 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaRegisterInfo.cpp | 4 |
2 files changed, 3 insertions, 4 deletions
diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp index 1e360676b6..e51b78457b 100644 --- a/lib/Target/Alpha/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp @@ -97,8 +97,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { O << RI.get(MO.getReg()).Name; return; - case MachineOperand::MO_SignExtendedImmed: - case MachineOperand::MO_UnextendedImmed: + case MachineOperand::MO_Immediate: std::cerr << "printOp() does not handle immediate values\n"; abort(); return; diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 85c9da8e64..95f60ed2e6 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -234,14 +234,14 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { //inst off the SP/FP //fix up the old: MI.SetMachineOperandReg(i + 1, Alpha::R28); - MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, + MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, getLower16(Offset)); //insert the new MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { - MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset); + MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset); } } |