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author | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
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committer | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
commit | c23197a26f34f559ea9797de51e187087c039c42 (patch) | |
tree | bf497ec9a02cd2fc0b64e3e58eff037a719a854d /lib/Target/CellSPU/SPUISelLowering.cpp | |
parent | 1f316e321a8f2fa0e193c5444584a67a8aabe9a8 (diff) | |
download | llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.gz llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.bz2 llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.xz |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPUISelLowering.cpp')
-rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 6b9df67d6c..2042a93e91 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -875,7 +875,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } } - LLVM_UNREACHABLE("LowerConstantPool: Relocation model other than static" + llvm_unreachable("LowerConstantPool: Relocation model other than static" " not supported."); return SDValue(); } @@ -906,7 +906,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } } - LLVM_UNREACHABLE("LowerJumpTable: Relocation model other than static" + llvm_unreachable("LowerJumpTable: Relocation model other than static" " not supported."); return SDValue(); } @@ -1138,7 +1138,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); switch (Arg.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ValueType for argument!"); + default: llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i8: case MVT::i16: case MVT::i32: @@ -1270,7 +1270,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // If the call has results, copy the values out of the ret val registers. switch (TheCall->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ret value!"); + default: llvm_unreachable("Unexpected ret value!"); case MVT::Other: break; case MVT::i32: if (TheCall->getValueType(1) == MVT::i32) { @@ -1738,7 +1738,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { } else if (EltVT == MVT::i64 || EltVT == MVT::f64) { V2EltIdx0 = 2; } else - LLVM_UNREACHABLE("Unhandled vector type in LowerVECTOR_SHUFFLE"); + llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE"); for (unsigned i = 0; i != MaxElts; ++i) { if (SVN->getMaskElt(i) < 0) @@ -1834,7 +1834,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { // Create a constant vector: switch (Op.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected constant value type in " + default: llvm_unreachable("Unexpected constant value type in " "LowerSCALAR_TO_VECTOR"); case MVT::v16i8: n_copies = 16; VT = MVT::i8; break; case MVT::v8i16: n_copies = 8; VT = MVT::i16; break; @@ -1853,7 +1853,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { } else { // Otherwise, copy the value from one register to another: switch (Op0.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected value type in LowerSCALAR_TO_VECTOR"); + default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR"); case MVT::i8: case MVT::i16: case MVT::i32: @@ -1880,13 +1880,13 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { // sanity checks: if (VT == MVT::i8 && EltNo >= 16) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15"); else if (VT == MVT::i16 && EltNo >= 8) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7"); else if (VT == MVT::i32 && EltNo >= 4) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4"); else if (VT == MVT::i64 && EltNo >= 2) - LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2"); + llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2"); if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) { // i32 and i64: Element 0 is the preferred slot @@ -2065,7 +2065,7 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, assert(Op.getValueType() == MVT::i8); switch (Opc) { default: - LLVM_UNREACHABLE("Unhandled i8 math operator"); + llvm_unreachable("Unhandled i8 math operator"); /*NOTREACHED*/ break; case ISD::ADD: { @@ -2585,7 +2585,7 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) cerr << "*Op.getNode():\n"; Op.getNode()->dump(); #endif - llvm_unreachable(); + llvm_unreachable(0); } case ISD::LOAD: case ISD::EXTLOAD: |