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authorChandler Carruth <chandlerc@gmail.com>2012-04-23 18:25:57 +0000
committerChandler Carruth <chandlerc@gmail.com>2012-04-23 18:25:57 +0000
commitd410eaba04211d53a523a518a5e315eb24c1072f (patch)
tree4f1dce3ce0466afddc686b95b2432690f3086b95 /lib/Target/Hexagon/HexagonInstrInfo.h
parent15e56ad8855ff2d135a79efa71b540852acf3b97 (diff)
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Revert r155365, r155366, and r155367. All three of these have regression
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfo.h')
-rw-r--r--lib/Target/Hexagon/HexagonInstrInfo.h18
1 files changed, 3 insertions, 15 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h
index 9682c05ea1..730687036c 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -107,8 +107,6 @@ public:
unsigned createVR(MachineFunction* MF, MVT VT) const;
- virtual bool isExtendable(const MachineInstr* MI) const;
- virtual bool isExtended(const MachineInstr* MI) const;
virtual bool isPredicable(MachineInstr *MI) const;
virtual bool
PredicateInstruction(MachineInstr *MI,
@@ -138,10 +136,6 @@ public:
isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
const BranchProbability &Probability) const;
- unsigned getInvertedPredicatedOpcode(const int Opcode) const;
- unsigned getImmExtForm(const MachineInstr* MI) const;
- unsigned getNormalBranchForm(const MachineInstr* MI) const;
-
virtual DFAPacketizer*
CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const;
@@ -166,16 +160,10 @@ public:
bool isS8_Immediate(const int value) const;
bool isS6_Immediate(const int value) const;
- bool isConditionalTransfer(const MachineInstr* MI) const;
- bool isConditionalALU32(const MachineInstr* MI) const;
- bool isConditionalLoad(const MachineInstr* MI) const;
- bool isConditionalStore(const MachineInstr* MI) const;
+ bool isConditionalALU32 (const MachineInstr* MI) const;
+ bool isConditionalLoad (const MachineInstr* MI) const;
bool isDeallocRet(const MachineInstr *MI) const;
- bool isNewValueJumpCandidate(const MachineInstr *MI) const;
- bool isNewValueJump(const MachineInstr* MI) const;
- bool isNewValueStore(const MachineInstr* MI) const;
- bool isPostIncrement(const MachineInstr* MI) const;
- bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
+ unsigned getInvertedPredicatedOpcode(const int Opc) const;
private:
int getMatchingCondBranchOpcode(int Opc, bool sense) const;