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authorBill Wendling <isanbard@gmail.com>2013-06-07 07:04:14 +0000
committerBill Wendling <isanbard@gmail.com>2013-06-07 07:04:14 +0000
commit41e632d9e1a55d36cb08b0551ad82a13d9137a5e (patch)
tree52d4b47f777e9928012d6028eefa27bedf9f4a12 /lib/Target/Mips/Mips16RegisterInfo.h
parented8b5b55a4416286758c5567c2602d2c7d0be585 (diff)
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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips16RegisterInfo.h')
-rw-r--r--lib/Target/Mips/Mips16RegisterInfo.h4
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/Mips/Mips16RegisterInfo.h b/lib/Target/Mips/Mips16RegisterInfo.h
index 2b3d2b1a4e..13e82a3ffb 100644
--- a/lib/Target/Mips/Mips16RegisterInfo.h
+++ b/lib/Target/Mips/Mips16RegisterInfo.h
@@ -20,10 +20,8 @@ namespace llvm {
class Mips16InstrInfo;
class Mips16RegisterInfo : public MipsRegisterInfo {
- const Mips16InstrInfo &TII;
public:
- Mips16RegisterInfo(const MipsSubtarget &Subtarget,
- const Mips16InstrInfo &TII);
+ Mips16RegisterInfo(const MipsSubtarget &Subtarget);
bool requiresRegisterScavenging(const MachineFunction &MF) const;